This work presents a new, simple method of measuring the generation lifetime in silicon-on-insulator (SOI) MOSFETs. Lifetime is extracted from the transient characteristics of MOSFET subthreshold current. Using this technique, generation lifetime was mapped across finished SIMOX (Separation by IMplantation of OXygen) wafers and BESOI (Bonded and Etchedback SOI) wafers. BESOI material evaluated in this study had about seven times longer effective generation lifetime than SIMOX material and both the SIMOX and the BESOI are shown to have a lifetime variation of /spl plusmn/10% across four inch wafers.
ArF excimer laser(λ=193nm) lithography is emerging following KrF DUV lithography(λ=248nm ). 193nm lithography has proven its potential for feature sizes down to 0.15μmlines/spaces patterns using high NA(O.6) because of resolution improvement. However, in practical use of ArF technology, there are problems involved in the properties of photoresist. To solve these problems, we synthesized ArF polymer resin, poly(2- (2-hydroxyethyl) carboxylate-5-norbornene / 2-t-butylcarboxylate-5-norbornene/2-carboxylic acid-5-norbomene/Maleic anhydride), all of the main chains are composed of alicyclic unit. 2-(2-Hydroxyethyl) carboxylate-5-norbornene was found as a very suitable adhesion promoter. Using this resist, 0.15μm L/S pattern was obtained at 14mJ/cm2 doses, using an ArF stepper on the developer, 2.38wt% tetramethyl ammonium hydroxide aqueous solution.
A concurrent hardware software codesign environment, PeaCE, is presented in this paper. PeaCE provides the designer with an environment in which the designer can design hardware and software components in a concurrent and cooperative manner. PeaCE covers the codesign which consists of specification, algorithm validation, partition, cosimulation, synthesis, and testing on prototyping board. The codesign workflow shown in this paper is demonstrated with 16-QAM modulation example.
The growing gap between processor and memory speeds makes memory issues a major bottleneck in the design of systems-on-silicon. When the system is designed for a targeted application (as is the case with embedded systems-onsilicon), several strategies can be employed to resolve this memory bandwidth bottleneck, including reorganization of data, exploiting locality of reference to tune the memory hierarchy, and intelligent partitioning of data amongst different levels of the memory hierarchy. From a system designer’s perspective, this requires an early memory exploration capability in order to evaluate its effects on system performance, cost and power, before the tasks of hardware and software co-design are performed. The research problems at this level require integration of the traditionally disjoint fields of computer architecture, compiler design, and digital CAD. This paper describes some strategies for memory organization and exploration that will aid system-level designers for future embedded systems-on-silicon.
The partial scan test method has a hidden overhead of data holding during scan shifting. The authors argue that the overhead is avoidable and demonstrate this by presenting a partial scan test method which consists of an FAN-based sequential ATPG algorithm and an ATPG-based partial scan selection algorithm.
A new Monte Carlo simulator for low energy electron beam lithography was developed, which includes discrete energy loss models to represent secondary electron generation and straggling effects in energy loss. The models are based on the Moller cross-section, the Vriens cross-section, and the plasmon excitation for inelastic scattering. The results of the new simulator were compared with those of the conventional model based on the screened Rutherford cross-section and the Bethe equation. With the new simulator, straggling effects are shown and more energy is deposited near the resist surface as compared to the conventional model. In addition, the simulated profiles are well matched with experiments.
It has presented the statistical performance from a focus on the minimum gate length of 0.8 /spl mu/m devices and CMOS ICs. The CMOS performances based on intra-die statistics have been statistically evaluated through experimental data gathered from four-type CMOS circuits. Most of measurements indicate higher speeds and larger powers at the edge positions of the wafer than at the central ones of the wafer, checking for real process maturity by discerning any outliers of the spec range which is speculated from variations as percentiles. This relationship of tradeoff between speed and power at those positions is true when the gate oxide thickness varies. Further, mixed-mode current-mirror CMOS circuit shows the large variations because of the poly resistor which separates the bias between MOSFET transistors.
