The advent of the Internet of Things (IoT) has revolutionised the way devices connect to each other, but it has also brought with it significant security concerns. Intrusion detection systems (IDS) have been deployed as a countermeasure against the increasing number of cyber attacks on IoT devices. Machine learning algorithms have shown promising capabilities in detecting these attacks. In this research paper, we present a comprehensive performance analysis of different machine learning algorithms used in IoT intrusion detection systems. Specifically, we evaluate six different algorithms: Logistic Regression, K-Nearest Neighbours, Decision Tree, Random Forest, Gradient Boosting and XGBoost. Our evaluation focuses on their effectiveness in detecting fraudulent activities in the IoT domain. Several evaluation metrics such as accuracy, precision, recall, F1 score and Matthews correlation coefficient are used to assess performance. This comprehensive analysis helps improve IoT security and provides valuable insights into the efficiency of machine learning algorithms for intrusion detection. Our experimental results highlight the outstanding performance of the Random Forest model on all evaluation metrics.
Voice activity detection (VAD), is a signal processing technique used to determine whether a given speech signal contains voiced or unvoiced segments. VAD is used in various applications such as Speech Coding, Voice Controlled Systems, speech feature extraction, etc. For example, in Adaptive multi-rate (AMR) speech coding, VAD is used as an efficient way of coding different speech frames at different bit rates. In this paper, we implemented the application of a Zero-Phase Zero Frequency Resonator (ZP-ZFR) as VAD on hardware. ZP-ZFR is an Infinite Impulse Response (IIR) filter that offers the advantage of requiring a lower filter order, making it suitable for hardware implementation. The proposed system is implemented on the TIMIT database using the Nexys Video Artix-7 FPGA board. The hardware design is carried out using Vivado 2021.1, a popular tool for FPGA development. The Hardware Description Language (HDL) used for implementation is Verilog. The proposed system achieves good performance with low complexity. Therefore this work is implemented on hardware, which can be used in various applications.
Hyperspectral data plays a crucial role in various fields, including remote sensing, environmental monitoring and medical imaging. With the increasing importance of hyperspectral data, the need for secure transmission and storage has become imperative. Protecting the ownership and integrity of hyperspectral data is essential to prevent unauthorized access and ensure its reliability. This paper presents a novel approach to address these challenges by introducing a secure and efficient reversible watermarking method for ownership protection. The proposed method embeds ownership information into the hyperspectral data without affecting the spectral information. The technique involves three steps: embedding, extraction and restoration, and enables reversible watermark removal. The performance of the method is evaluated using metrics such as Peak Signal-to-Noise Ratio (PSNR), Structural Similarity Index (SSIM) and Normalized Correlation (NC) and shows high ownership protection while maintaining visual quality and fidelity. The experimental results confirm the effectiveness of the proposed technique and show its robustness to various attacks and computational efficiency. This research helps preserve the integrity of hyperspectral data and provides a reliable solution for property protection in critical decisionmaking applications.
WebRTC videoconferencing has risen to prominence in recent years with a sharp increase in remote work and communication. Conferences with large numbers of participants and/or high-quality video streams can overload network and CPU resources and degrade performance, limiting the use of the technology. Several partial solutions exist to mitigate these issues, such as simulcast and Scalable Video Coding (SVC), but these solutions have shortcomings and require trade-offs that make them inadequate for some scenarios. We propose Demand-Aware Adaptive Streaming (DAAS), a novel method of increasing network and CPU efficiency that reduces stream quality—and thus resource consumption—at the source when possible. The method entails using WebRTC data channels to track the presented resolution of each video stream and adapting stream quality to match presentation requirements. The video publisher maintains full quality when required and adaptively reduces quality when possible. We show that the proposed method has advantages over existing methods in that it reduces network bandwidth and CPU requirements for all participants—senders and receivers—in a WebRTC videoconference.
Cognitive radio can be considered as a viable frequency access framework that overcomes the disadvantages of the licensed-based transmission procedure by allowing the secondary users to access the spectrum to transmit their data. However, due to the evolution of latency-sensitive real-time communication applications such as gaming and extended reality, it becomes more vital that cognitive radio networks should be studied with latency requirements on the data transmission. Recently, Age of Information has introduced itself as a important metric for evaluating the freshness of the transmitted data. In this paper, we investigate the latency and stability analysis of a two-user cognitive radio network that consists of one primary user, one secondary user and their destinations. The latency requirements of the transmitted data packets are taken into consideration by imposing Age of Information constraints on the data transmission of the users. We present two optimization problems, in the first problem, the secondary user stable throughput is maximized under an Age of Information constraint imposed on the data transmission of the secondary user. While, in the second problem, we maximize the stable throughput of the secondary user with respect to Age of Information constraints set on the data transmission of both the primary and secondary users. The resultant problems are found to be non-linear programming optimization problems. An appropriate algorithm is used to solve the problems and provide the numerical solutions. Our results characterize the impact of setting Age of Information constraints on the stability region of the network; we demonstrate that the stability region, in certain cases, is reduced by only 11% with strict Age of Information restrictions if compared to the scenario where no latency requirements is considered. Our results also show the potential accuracy of the algorithm adopted in this paper to solve the formulated optimization problems.
Continued growth and adoption of the Internet of Things (IoT) has greatly increased the number of dispersed resources within both corporate and private networks. IoT devices benefit the user by providing more local access to computation and observation compared to dedicated servers within a centralized data center. However, years of lax or nonexistent cybersecurity standards leave IoT devices as easy prey for hackers looking for easy targets. Further, IoT devices normally operate at the edge of the network, far from sophisticated cyberattack detection and network monitoring tools. When hacked, IoT can be used as a launching point to attack more sensitive targets or can be collected into a larger botnet. These botnets are frequently utilized for targeted Distributed Denial of Service (DDoS) attacks against service providers and servers, decreasing response time or overwhelming the system. In order to protect these vulnerable resources, we propose an edge computing system for detecting active threats against local IoT devices. Our system will utilize deep learning, specifically a Convolutional Neural Network (CNN) for detecting attacks. Incoming network traffic will be converted into an image before beings supplied to the CNN for classification. The network will be trained using the N-BaIoT dataset. Since the system is designed to operate at the edge of the network, it will run on the Jetson Nano for real-time attack detection.
Continued adoption of the Internet of Things (IoT) redefines the paradigm of network architectures. Historically, network architectures relied on centralized resources and data centers. The introduction of the IoT challenges this notion by placing computing resources and observation at the edge of the network. As a result, decentralized approaches for information processing and gathering can be adopted and explored. However, this shift greatly expands the network footprint and shifts traffic away from the center of the network, where observation and cybersecurity monitoring tools are frequently located. Further, IoT devices are often computationally constrained, limiting their readiness to deal with cyber-threats. These security vulnerabilities make the IoT an easy target for hacking groups and lead to the proliferation of zombie networks of compromised devices. Frequently, zombie networks, otherwise known as botnets, are coordinated to attack targets and overload network resources through a Distributed Denial of Service (DDoS) attack. In order to crack down on these botnets, it is essential to develop new methods for quickly and efficiently detecting botnet activity. This study proposes a novel botnet detection technique that first pre-processes network data through computer vision and image processing. The processed dataset is then sent to a neural network for final classification. Two neural networks will be explored, a sequential model and an auto-encoder model. The application of image processing has two advantages over current methods. First, the image processing is simple enough to be completed at the edge of the network by the IoT devices. Second, preprocessing the data allows us to use a shallower network, decreasing detection time further. We will utilize the N-BaIoT dataset and compare our findings to their results.
There are an increasing diversity of devices and networks for making and receiving video and/or audio calls. The prevalence of smartphones, multiple smart speakers and various computing platforms in many homes has led to much greater flexibility in how and where users communicate. This trend is only set to continue as AR/VR becomes more commonplace and services such as healthcare, for which flexib...
The prompt γ-ray neutron activation analysis (referred PGNAA) technology is a use of the strong penetrating power of neutron and γ-ray, which can get the whole information of the elements inside a thick material. Therefore, the PGNAA technology has become the best choice to meet the needs of detecting the composition of industrial materials. This paper presents a data acquisition scheme for the physical targets of PGNAA, which has a high pass rate, high SNR and can analyze and process a large number of pulses which the detector outputs. This system is designed to rapidly analyze the composition and content of the industrial materials in real-time. Since we have to dynamically analyze the moving materials, the expected time for a measurement can not exceed 120s, The average counting rate is expected to reach more than 500kc/s.
The Unified Communication Framework is a unified network protocol and FPGA firmware for high speed serial interfaces employed in Data Acquisition systems. It provides up to 64 different communication channels via a single serial link. One channel is reserved for timing and trigger information whereas the other channels can be used for slow control interfaces and data transmission. All channels except the timing are bidirectional and share network bandwidth according to assigned priority. The timing channel distributes messages with fixed and deterministic latency in one direction. In this regard the protocol implementation is asymmetric. The precision of the timing channel is given by the jitter of the recovered clock and is typically in the order of 10-20 ps RMS. The timing channel has highest priority and a slow control interface should use the second highest priority channel in order to avoid long delays due to high traffic on other channels. The framework supports point-to-point connections and star-like 1:n topologies for optical networks with a passive splitter. It always employs one of the connection parties as a master and the others as slaves. The starlike topology can be used for front-ends with low data rates or pure time distribution systems. In this case the master broadcasts information according to assigned priority whereas the slaves communicate in a time sharing manner to the master. In the OSI layer model the Unified Communication Framework can be classified as layers one to three which includes the physical, the data, and the network layer.
XENON1T is a next generation Dark Matter search experiment using 3.5 tons of liquid xenon for direct detection of Dark Matter. A dual-phase liquid xenon Time Projection Chamber (TPC) shielded below 1400m of rock at the Gran Sasso underground laboratory in Italy serves as both target and detector. The TPC is inside a 10m high by 9.5m diameter water Cherenkov detector serving as an active muon veto. The Slow Control system is based on industrial process control hardware and software. It is now being used to commission the detector. The system provides secure monitoring and control by collaborators, shifters and experts at both local and remote locations. 3.5 tons of liquid xenon requires extreme care to guard the safety of the instrumentation and to prevent the loss of any of the high value xenon. The system consists of a distributed architecture of networked local control units with touch panels for local control. Critical operations can be guarded by requiring specific conditions to be satisfied before they are allowed to be executed. Two Supervisory Control And Data Acquisition (SCADA) computers provide active-passive redundancy. All operating parameters and their history are stored and can be displayed. Alarm messages are sent by email, cellular network and by pre-recorded voice over land telephone lines. Experience with both the benefits and the disadvantages of using industrial process control hardware and software are presented.
Laser calibration facilities play a key role in the study and characterization of detectors like electromagnetic or hadronic calorimeters. They can be operated both during physics data taking and off run. Typically these facilities are based on a lasers source which deliver light to each detector element via a light distribution system. The laser control system typically manages the interface between the experiment and the laser source, allowing the generation of light pulses according to specific needs as detector calibration, study of detector performance in running conditions, evaluation of DAQ performance. Any specific implementation depends on hardware features. As an example light pulses could be generated according to a physics distribution as it appens in physics run or real data taking. In this case light pulses should be generated according to a pattern which follows a programmable function and changes on a statistical base event by event. In this work we present a laser control system for calibration of a calorimeter. It is a custom solution based on an hybrid platform hosting an FPGA and an ARM processor. We present the system architecture and the performances of a preliminary implementation.
In the ETOF(End-cap TOF) upgrade of BESIII, MRPC(Multi-gap Resistive Plate Chamber) detectors are used. ETOF is designed with 72 MRPCs. 24 channels signal are read out from each MRPC, in which 6 neighbouring channels OR together in Front-End Electronic(FEE) side. So 288 channel hit signals are sent to ETOF trigger system for trigger logic. The MPRC hit signal is about 30 ns width after FEE. Hit signals are stretched and trigger data are stored by TDPP (Trigger Data Pre-Processor) and then sent to ETOFT (End-cap TOF Trigger) through 10 high speed optical fiber links. Trigger data are aligned and stored in FIFO in ETOFT. Trigger logic in the center FPGA counts hit signals and finds Back to Back (BtB) events and give out three ETOF trigger conditions: NETOF.GE.1, NETOF.GE.2 and ETOF.BB. ETOF trigger conditions are integrated with other detector trigger signals by SIF2(Signal Integrate and Fan-out Version2) to Global Trigger to generate L1. ETOF trigger system was installed on BESIII in Sept.2015 and has run stable for half year.
With the purpose of realizing an amplifier capable to process large dynamic range signals, a programmable gain range amplifier that comprises of attenuator, variable gain amplifier, differential amplifier is developed. This amplifier has a programmable gain from -20 dB to 33 dB and a DC to 700 MHz bandwidth. Besides, remote programmability makes this amplifier convenient to use. To test its feature in signal conditioning, a BaF2 detector signal is amplified and results show good performance. This amplifier has promising application possibility in high-speed large dynamic signal processing situations, especially in those system requires accurate signal conditioning like ultra-fast ADC system.
The superconducting stellarator Wendelstein 7-X (W7-X) started plasma operation in December 2015 after the commissioning phase of the machine. The main technical and diagnostic systems have been finished successfully. The timing system is an important part of the Control, Data Acquisition and Communication systems of W7-X. The first version of the TTE-system is in routine operation at the W7-X experiment. Since 2004 it has been used for the commissioning of the control and data acquisition components, and also for the stellarator WEGA. The commission of the second version of the TTE-system is still on going and planned to be finished end of 2016. Starting with an introduction of the TTE-system of W7-X, this contribution describes the main features of the TTE-system. The actual state of the TTE-system and the network topology will be presented. Finally, first experiences of W7-X operational phase OP1.1 related to the TTE-system are discussed.
Modern digital low level radio frequency (LLRF) control systems used to stabilize the accelerating field in facilities such as Free Electron Laser in Hamburg (FLASH) or European X-Ray Free Electron Laser (E-XFEL) are based on the Field Programmable Gate Array (FPGA) technology. Presently these accelerator facilities are operated with pulsed RF. In future, these facilities should be operated with continuous wave (CW) which requires significant modifications on the real-time feedbacks realized within the FPGA. For example, higher loaded quality factor of the cavities when operated in a CW mode requires sophisticated resonance control methods. However, iterative learning techniques widely used for machines operated in pulsed mode are not applicable for CW. In addition, the mechanical characteristic of the cavities have now a much more important impact on the choice of the feedback scheme. To overcome the limitations of classical PI-controllers novel real-time adaptive feed forward algorithm is implemented in the FPGA. Also, the high power RF amplifier which is an inductive output tube (IOT) for continuous wave operation instead of a klystron for the pulsed mode has major impact on the design and implementation of the firmware for regulation. In this paper, we report on our successful approach to control multi-cavities with ultra-high precision (dA/A<0.01%, dphi<0.02 deg) using a single IOT source and individual resonance control through piezo actuators. Performance measurements of the proposed solution were conducted at Cryo Module Test Bench (CMTB) facility.
Interlocks are the instrumented functions of ITER that protect the machine against failures of the plant system components or incorrect machine operation. Regarding I&C, the Interlock Control System (ICS) ensures that no failure of the conventional ITER controls can lead to a serious damage of the machine integrity or availability. The ICS is in charge of the supervision and control of all the ITER components involved in the instrumented protection of the Tokamak and its auxiliary systems. It is constituted by the Central Interlock System (CIS), the different Plant Interlock Systems (PIS) and its networks. The ICS does not include the sensors and actuators of the plant systems but it is in charge of their control. The ITER interlock system shall be designed, built and operated according to the highest quality standards. The international standard IEC-61508 has been chosen as the reference. In both CIS and PIS cases two main architectures are used: a slow architecture, for those functions with response time requirements slower than 100ms (300 ms for central interlock functions), based on PLC technologies, and a fast architecture, based on FPGA technologies, for the functions with faster requirement times. The proposed design for fast PIS is based on the use of RIO (Reconfigurable Input/Output) technology from National Instruments (compactRIO platform). In order to provide a high integrity solution, a FMEDA (Failure Modes Effects and Diagnostics Analysis) has been conducted to analyze the components behavior. According to the output of the FMEDA a set of diagnostics has been defined and additional redundancy was added to the architecture to improve the integrity figures. The defined configuration has been called the “double-decker solution”, with two chassis running in parallel, communicated between them using a synchronous high speed serial line, and using redundant modules to implement the input and output measurement/excitations and redundant analog and digital modules to implement the diagnostics of these input/output modules. The integrity figures for the “double decker” solution are obtained from the classification of the failure rates, obtaining for the different configurations a SFF (safe failure fraction) of 85% and a FPH (Probability of dangerous Failure per Hour) of less than 1E-07. The FPGA design includes all the hardware to support the data acquisition from the input modules, the implementation of the diagnostics functionalities for analog and digital modules, the voting schema and the activation/deactivation of digital outputs. The platform includes an external test platform, also based on compactRIO technology, to perform the validation of the system and to register the performance of the different interlock functions implemented. The response times obtained for the TTL input to TTL output interlock function ranges from 5μs to 20μs; for the analog input to TTL output the response time is in the range of 41 μs to 90 μs, and for interlock functions using 24V digital input to 24V digital output, the time can rise up to 643 μs.
Feature extraction is a data pre-processing stage of the Transition Radiation Detector (TRD) data-acquisition chain (DAQ) as part of the Compressed Baryonic Matter (CBM) experiment. The feature extraction stage delivers event-filtered and bandwidth-reduced data to the First Level Event Selector (FLES). The feature extraction stage implements multiple processing algorithms in order to find and extract regions of interest within time series signals. Algorithms such as peak-finding, signal integration, center of gravity and time-over threshold were implemented for online analysis. On the other hand, a local clustering algorithm allows to find cluster members and to implement even further data reduction algorithms. A feature extraction framework for automatic firmware generation has been tested for the CBM-TRD data acquisition chain. The framework allows the generation of Field Programmable Gate Array (FPGA) designs that implement feature extraction algorithms. Such designs are FPGA-platform independent and are described by a file written in a Domain Specific Language (DSL). The result of using the mentioned feature extraction framework for the TRD feature extraction stage is presented and discussed.
The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment at the Large Hadron Collider (LHC). The upgraded High Luminosity LHC will deliver five times the current nominal instantaneous luminosity. The ATLAS Phase II upgrade will upgrade the readout electronics of the TileCal for the HL-LHC. The majority of the front- and back-end electronics will be redesigned with a new readout strategy. In the upgraded readout architecture for Phase II, the frontend electronics consist of the Front-End Boards, Main Boards and the Daughter Boards. The Main Board digitizes the analog signals coming from the Front-End Boards (FEBs) connected to the PhotoMultiplier Tubes (PMTs), provides integrated data for minimum bias monitoring and includes electronics for PMT calibration. Three different FEB options with different signal acquisition strategies are under study: new 3-in-1 cards, QIE chip and FATALIC chip. The Daughter Board receives and distributes Detector Control System commands, clock and timing commands to the rest of the elements of the front-end electronics, as well as collects and transmits the digitized data to the backend electronics at the LHC frequency (~25 ns). In the back-end electronics, the TileCal PreProcessor (TilePPr) receives and stores the digitized data from the Daughter Boards in pipeline memories to cope with the latencies and rates specified in the new ATLAS DAQ architecture. The TilePPr interfaces between the data acquisition, trigger and control systems and the front-end electronics. In addition, the TilePPr distributes the clock and timing commands to the frontend electronics for synchronization with the LHC clock.
The beam-based feedback system is essential for the operation of the LHC. It comprises two C++ servers: a FESA-based (framework for real-time systems developed at CERN) acquisition and configuration proxy, and a non FESA-based controller which sanitises the acquisition data and feeds it to multiple real-time feedback algorithms (orbit control, radialloop control and tune control) ensuring a stable orbit of the LHC's beams. Responsibility for the further development and maintenance of the servers was recently transferred to a new team, who have made considerable efforts to document the existing system as well as improve its operational reliability, performance, maintainability and compliance with CERN's software and operational standards. Software changes are accompanied by rigorous unit-testing with future releases tested outside the operational environment, thus minimizing the potential for beam downtime. This approach has proven very effective during re-commissioning for LHC's run 2, where the systems underwent significant changes. In a bid to homogenize operational procedures for configuring LHC systems, a demand to improve the real-time configuration of the system's feedback references and optics was identified. To replace the existing ad-hoc method of real-time configuration, a new waveform-based server, pre-configured with sequences of N-dimensional values versus time, autonomously ensures that the system is re-configured at precisely the correct time. This paper describes the design choices, software architecture, integration and preliminary testing of the new waveform-based server. In particular, considerable effort was put into reducing the impact of changing already established and tested behaviour.
