Public-space surveillance produces large volumes of video that can be difficult for personnel to review promptly. This paper presents Spot Crime, a prototype surveillance-support system that combines face detection, CNN-based embedded facial feature representation, database-based similarity matching, and alert generation in a web application. The proposed pipeline accepts CCTV frames or uploaded images, preprocesses the input, detects and aligns facial regions, generates facial embeddings, and compares them with authorized reference records. When a similarity score exceeds a threshold validated for the selected model and operating conditions, the system creates a preliminary alert containing the timestamp, camera identifier, candidate score, and reference-record identifier for review by authorized personnel. OpenCV and dlib support image processing and face localization, while Python/PHP and MySQL provide application and record-management functions. Unlike a system that labels a person as a criminal, the proposed design treats a match only as a candidate identity association; it does not establish guilt, and human verification remains essential. The paper details the architecture, workflow, database structure, operational safeguards, and an evaluation framework. Since quantitative benchmark results are not provided in the current manuscript, claims about accuracy, latency, and field effectiveness are treated as objectives for future validation rather than established outcomes. The principal contribution is an integrated design for traceable candidate matching and alert review, with explicit attention to false matches, demographic performance, privacy, and responsible operational use.
Thermoelectric power measurements were conducted on polycrystalline Ti- and Zr-substituted Mn–Zn ferrites, and the corresponding Seebeck coefficient, carrier concentration, and drift mobility were analyzed. The Seebeck coefficient increased steadily with temperature, attaining peak values near 450 K for Ti-substituted samples and 440 K for Zr-substituted samples. All compositions exhibited n-type conduction across the entire temperature range investigated. At elevated temperatures, the ferrites demonstrated non-degenerate semiconducting behavior, indicative of thermally activated charge transport. The conduction mechanism is predominantly governed by electron hopping between Fe²? and Fe³? ions, in agreement with the presence of narrow energy bands and localized electronic states. The temperature-dependent behavior of drift mobility can be explained using the wavy-band model, which accounts for variations in the density of states affecting carrier transport.
Advanced composite materials have become very important in high-performance electronic applications due to their capability of offering variable electric conductivity, high thermal stability, great mechanical strength, lightweight structure, and enhanced electromagnetic interference (EMI) shielding capacity. Possibilities of using polymer-matrix composite, ceramic composites, carbon-based nano-composites, and hybrid-nanofiller composites exist as possible means of circumventing the constraints faced in using conventional electronic packaging and heat dissipation materials. Conventional composite-material design depends greatly on trial and error, empirical formulation, and optimization of individual parameters. Such a process hinders the efficient identification of suitable matrix-reinforcement pairing, appropriate concentration of fillers, interfacial characteristics, and processing variables. Improving the material’s thermal conductance could result in weakening of its electrical insulation, flexibility, and mechanical stability, thereby creating a multi-objective optimization problem. A new methodological framework of Advanced Composite Intelligence and Multi-objective Optimization (ACIMO), which utilizes artificial intelligence (AI), materials property prediction, and multi-objective evolutionary optimization, is proposed. The framework takes into account the material composition, reinforcement geometry, filler concentration, interfacial characteristics, and fabrication conditions to estimate thermal conductivity, electrical resistivity, tensile strength, and EMI shielding efficiency.
The IEEE-754 single-precision floating-point multiplication is a fundamental arithmetic operation in modern digital systems and is widely used in DSP, graphics and machine learning accelerators. The demand for computations is increasing day by day, so the hardware realization of these operations in terms of logic utilization and signal propagation delay is of utmost importance. This paper presents a highly optimized design of 32-bit floating point multiplier for FPGA. The design approach is purely structural with high emphasis on mantissa data-path. The proposed architecture uses a highly specialized Radix-4 Modified Booth Encoding algorithm to reduce the number of partial products by half. This leads to a substantial reduction of hardware overhead. We also propose a new narrow 25-bit Partial Product Generator and a dedicated wire-routed Two-Shift stage, which achieves around 50% gate reduction in the generation phase by eliminating redundant sign-extensions. A bounded Dadda reduction tree compresses the first 14-row matrix (13 partial products and one structural sign-correction row). The proposed tree is approximately 41% narrower than conventional 88-bit designs, thereby reducing internal interconnect and routing overhead. The last addition is done by 52-bit Carry Propagate Adder. The proposed architecture is synthesized on Xilinx Artix-7 platform and the results show the significant area saving and the deeply reduced latency, which makes the architecture very effective for high-performance computational applications with resource constraints.
FP-Floating point arithmetic unit is the widely used application in Digital Signal Processing (DSP), which is an alternative of the logarithmic number system. When compared to the square root operations, the addition, subtraction, multiplication and division are more challenging tasks. In accordance with this reason, few structures were developed in the existing literatures concerning the DSP. But, it has some drawbacks which includes increased memory usage, delay and power consumption. To overwhelm these issues, a Semi Parallel Folded Add-Shift (SPFAS) architecture is carefully designed by making use of minimized components is introduced. Here, the folded Discrete Tchebichef Transformation (DTT) multiplier is integrated with SPFAS forming the novelty in the circuit used in this work in order to find the output register. Moreover, there is no need to add any separate block for performing subtraction operation because of the integration undertaken. The main advantage of this concept is that it reduces the size of Digital Signal Processing (DSP) unit with minimum usage of logical components and registers. Also, the structure of shifter and adder are changed to reduce the accumulator size, Flip Flop (FF) and Look Up Table (LUT). In experiments, the performance of the proposed SPFAS with DTT architecture is evaluated and compared in terms of delay, area, latency, cycles, RAM, LUTs, slice and FFs. On investigating, we could infer that this devised architecture design need only lesser usage components of 5979 instead of 8702.
