This paper studies static-priority preemptive scheduling on a multiprocessor using partitioned scheduling. We propose a new scheduling algorithm and prove that if the proposed algorithm is used and if less than 50% of the capacity is requested then all deadlines are met. It is known that for every static-priority multiprocessor scheduling algorithm, there is a task set that misses a deadline although the requested capacity is arbitrary close to 50%.
Much research exists for the efficient processing of spatio-temporal data streams. However, all methods ultimately rely on an ill-equipped processor [22], namely a CPU, to evaluate concurrent, continuous spatio-temporal queries over these data streams. This paper presents GEDS, a scalable, Graphics Processing Unit (GPU)-based framework for the evaluation of continuous queries over spatio-temporal data streams. Specifically, GEDS employs the computation sharing and parallel processing paradigms to deliver scalability in the evaluation of continuous, spatio-temporal range queries and continuous, spatio-temporal kNN queries. The GEDS framework utilizes the parallel processing capability of the GPU, a stream processor by trade, to handle the computation required in this application. Experimental evaluation shows promising performance and shows the scalability and efficacy of GEDS in spatio-temporal data streaming environments. Additional performance studies demonstrate that, even in light of the costs associated with memory transfers, the parallel processing power provided by GEDS clearly counters and outweighs any associated costs.
Non-traditional safety-critical systems are widely used in transportation control, banking and financial systems, and the management of water systems, which have different characteristics with traditional safety-critical systems. In those systems, tasks cannot be determined as critical or non-critical apparently but a few failures of some tasks are acceptable. This paper establishes a new schedule model for Non-traditional safety-critical systems and proposes a non-preemptive fuzzy classification (NFC) algorithm. NFC is consisted of two phrases, called initialized step and execution step. Afterwards, NFC and MUF are compared based on sample tasks abstracted from an existing financial system. It is concluded that NFC has fewer failed tasks and similar performance.
The Multi-Level Computing Architecture MLCA is a novel parallel System-on-a-Chip architecture targeted for multimedia applications. It features a top level controller that automatically extracts task level parallelism using techniques similar to how instruction level parallelism is extracted by superscalar processors. This allows the MLCA to support a simple programming model that is similar to sequential programming. In order to assist programmers to easily and efficiently port multimedia applications to the MLCA programming model, a compilation environment is designed. This compilation environment enhances parallelism in MLCA programs by applying three simple code transformations that are based on known compiler optimizations. In this paper, we describe the MLCA architecture, its programming model, its compilation environment and an evaluation of its performance. Our experimental evaluation with three real multimedia applications and an MLCA simulator shows that the MLCA is a viable architecture and scaling speedups can be obtained using the compilation environment with little programmer effort.
We consider the problem of task reweighting in fair-scheduled multiprocessor systems wherein each task's processor share is specified as a weight. Task reweighting can be used as a means for consuming (or making available) spare processing capacity. In this paper, we propose a multiprocessor reweighting scheme that can change a task's processor share with "minimal" error per share change.
In real-time systems, an efficient and stable implementation of timer is crucial to the timing requirements of tasks. The traditional methods take O(n2) time overhead to maintain timers in the periodic task model. In this paper, we present a new implementation method that takes O(n) time overhead. This method calculates all trigger instants of periodic tasks within a hyperperiod off-line, and assigns these instants to corresponding periodic timers. The timer system checks whether a trigger instant arrives in the timer Interrupt Service Routine (ISR), and activates tasks periodically without any additional overhead, such as deletion and insertion for new timeouts. Experiments show that the method presented in this paper can improve the execution speed of timers with low overhead in space and increase stability in execution time.
The analysis and evaluation of the speed performance of personal computers for various classes of applications continues to be an important area of research. One such class of applications is that of embedded applications. Embedded applications such as VOIP, streaming video and image processing software etc. are used significantly in the personal computer domain. In this paper, we analyze the execution characteristics of a subset of widely used embedded applications on a general personal computer based on the Intel Pentium 4 microprocessor. It was observed that, for most of the applications chosen here, the combination of lower trace cache hit rates and lower L1 cache load hit rates may have a more adverse impact on the performance of this machine when compared to other parameters such as L2 cache load hit rates, branch prediction rates, etc. The overall L2 cache load hit rates, branch prediction rates and TLB hit rates were found to be fairly high. Hardware improvements over the trace cache and L1 cache structures of the chosen machine could help improve performance for many of these applications.
Much research exists for the efficient processing of spatio-temporal data streams. However, all methods ultimately rely on an ill-equipped processor [22], namely a CPU, to evaluate concurrent, continuous spatio-temporal queries over these data streams. This paper presents GEDS, a scalable, Graphics Processing Unit (GPU)-based framework for the evaluation of continuous spatio-temporal queries over spatio-temporal data streams. GEDS employs the computation sharing and parallel processing paradigms to deliver scalability in the evaluation of continuous spatio-temporal queries. The GEDS framework utilizes the parallel processing capability of the GPU, a stream processor by trade, to handle the computation required in this application. Experimental evaluation shows promising performance and shows the scalability and efficacy of GEDS in spatio-temporal data streaming environments.
This paper studies preemptive static-priority scheduling on multiprocessors. We consider two approaches: global pfair static-priority scheduling and partitioned traditional static-priority scheduling. We prove that if presented algorithms are used and if less than 50% of the capacity is used then all deadlines are met. It is known that no static-priority multiprocessor scheduling algorithm can achieve a utilization bound greater than 50%.
Fixed-task-priority (FTP) scheduling and earliest-deadline-first (EDF) scheduling policies are alike in fixing the priority of each job of a task at the time the job is released. This common feature of FTP and EDF scheduling permits a unified analysis of scheduling failures, to derive new sufficient tests for meeting all deadlines of a set of independent sporadic tasks under a global preemptive FTP or EDF scheduling policy. The performance of the new tests has been evaluated in comparison to prior schedulability tests, by simulation. The new tests are able to verify some schedulable task systems that could not be verified by prior tests, but also fail to verify some systems that can be verified by prior analysis techniques. The biggest gain appears to be for fixed-task-priority scheduling, especially with post-period deadlines.
This paper presents an effective approach using synchronous parallel transmission worm-switching supporting multicast services on hypercube multi-core architecture. Hypercube is a flexible interconnection structure and multi-cast packets on it are routed and scheduled among multi-cores using a local identity routing algorithm. The identity ID attached to every flit allows different flits to be mixed in the same queue. In internal nodes, LUT decides the direction of flits and RU records the transmitting direction. Then switch arbiter decides what can pass the outgoing links and what have to wait. Polling-transmission policy is used to solve the deadlock problem.
Delay jitter is a critical factor that must be considered in many real-time applications that require accurate prediction of packet delivery times. Delay jitter can be smoothed by holding packets in a play-back buffer for a certain time called a play-back delay. In this paper, we extensively examine the new scheme that we have proposed in [1] to enhance the prediction of the play-back delay in Networked Control Systems (NCSs). Our newly proposed scheme differs from previous schemes by using the one way delay variation that we have studied its behavior by conducting extensive measurements between fifty strategically located wired and wireless connected hosts. The advantages of our scheme are that it predicts sudden delay spikes, provides a closer approximation to the round trip time (RTT), and exhibits less frequent outliers.
This special issue consists of five manuscripts selected from the 2009 International Conference on Embedded Computing. All the papers took further review after extension. The first paper in this special issue is “A New Implementation Method of Timer for Periodic Tasks” by Zhigang Gao, Peifeng Zhang, Guojun Dai [1]. This work presents a new implementation of timer method for periodic tasks in real-time systems, called S-Method, which takes O (n) time overhead. While the traditional methods take O (
Interrupt latency has great impact on the real time and predictability of real-time operating system kernels. In traditional implementation of real-time kernels, interrupts are frequently disabled in system service routines, critical sections, etc., which causes kernel interrupt latency. In this paper we propose a method called PIL (predictive interrupt latency). PIL reduces interrupt latency by never disabling interrupts during any system service routines. Moreover, it makes interrupt latency vary little, which improves the predictability in the response time for external events. We have implemented the PIL method in a real-time kernel. Experimental results show PIL improves real time and predictability of real-time systems with low time and space overheads.
In modern digital ICs, the increasing demand for performance and throughput requires higher operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip clock signals with fast rise/fall times are among the most detrimental sources of electromagnetic (EM) noise, since not only they generate radiated emissions, but they also have a large impact con the conducted emissions, as the power rail noise localized in close proximity of the toggling clock edges propagates to the board through the power and ground I/O pads. In this work, we analyze the impact of different clock distribution solutions on the spectral content of typical on-chip waveforms, in order to develop an effective methodology for EMC-aware clock-tree synthesis, which globally reduces the EM emissions. Our approach can be seamlessly integrated into a typical design flow, and its effectiveness is demonstrated with experimental results obtained from the clock distribution network of an industrial digital design.
Previous research has shown that there are two architectures for speech-to-speech translation (S2ST) system implementation. One is client-server based systems that are built on the server computer, which means they are not available anytime or anywhere. The other is portable stand-alone devices, which lack real-time performance. Therefore, this work presents a hardware-software co-design of a speech translation embedded system for portable S2ST applications. This system is characterized by small size, low cost, real-time operation, and high portability. In order to realize the proposed S2ST system, we have designed the ARM-based system-on-a-programmable-chip (SoPC) architecture, the speech translation intellectual property, and the software procedures of the proposed SoPC. The entire design was implemented on ALTERA EPXA10. The English-to-Mandarin translation process can be completed within 0.5 second at a 40 MHz clock frequency with 1,200 translation patterns. The maximum frequency is 46.22 MHz, and the usage of logic elements is 19,318 (50% of the total number of logic elements of the EPXA10 device).
We are interested in the programming of real-time embedded control systems, such as in robotic, automotive or avionic systems. They are designed with multiple tasks, each with multiple modes. It is complex to design task handlers that control the switching of activities in order to insure safety properties of the global system. We propose a model of tasks in terms of transition systems, designed especially with the purpose of applying existing discrete controller synthesis techniques. This provides us with a systematic methodology, for the automatic generation of safe task handlers, with the support of synchronous languages and associated tools.
Modern embedded consumer devices execute complex network and multimedia applications that require high performance and low energy consumption. For implementing complex applications on Network-on-Chips (NoCs), a design methodology is needed for performing exploration at NoC system-level, in order to select the optimal application-specific NoC architecture, serving the application requirements in the best way. The design methodology we present in this paper is based on the exploration of different NoC characteristics and is supported by a flexible NoC simulator which provides the essential evaluation metrics in order to select the optimal communication parameters of the NoC architectures. We illustrated that it is possible with the evaluation metrics provided by the simulator we present, to perform exploration of several NoC aspects and select the optimal communication characteristics for NoC platforms having network and multimedia applications as the target domains. With our methodology we can achieve a gain of 57% in the Energy × Delay Product on average.
How to save energy is a critical issue for the life time of sensor networks. Under continuously changing environments, sensor nodes have varying sampling rates. In this paper, we present an online algorithm to minimize the total energy consumption while satisfying sampling rate with guaranteed probability. We model the sampling rate as a random variable, which is estimated over a finite time window. An efficient algorithm, EOSP (Energy-aware Online algorithm to satisfy Sampling rates with guaranteed Probability), is proposed. Our approach can adapt the architecture accordingly to save energy. Experimental results demonstrate the effectiveness of our approach.
Ensuring anonymity in wireless and hoc networks is a major security goal. Using traffic analysis, the attacker can compromise the network functionality by correlating data flow patterns to event locations/active areas. In this paper we present a novel Scalable Anonymous Protocol that hides the location of nodes and obscure the correlation between event zones and data flow from snooping adversaries. We quantify the anonymity strength of our protocol by introducing a new anonymity metric: Degree of Exposure Index. Our protocol is designed to offer flexible tradeoffs between degree of anonymity and communication-delay overhead.
