Multiplication dominates the computational cost and energy consumption of deep neural network (DNN) inference. This paper presents a novel bias-aware two-stage error compensation that generates structured families of approximate multipliers (AMs) with analytically controllable error bias and magnitude while maintaining uniform energy consumption within each family of AMs. Using a truncation-based signed multiplier as a base, the first compensation stage of the framework introduces deterministic binary compensation at the least significant bits to mitigate systematic underestimation without adding arithmetic logic or increasing switching activity. The second stage inserts a two-gate compensation circuit at the first column after truncation, supplying a fixed positive mean error that works in conjunction with the constant to drive the net mean bias error towards zero. The combination provides a unified closed-form design equation, from which any member of the family is fully characterised without simulation. The proposed AM designs are synthesized in a 45 nm technology and compared with state-of-the-art AMs using a comprehensive set of error metrics. All the multipliers are evaluated on LeNet-5, ResNet-14, VGG-16, and VGG-19 under INT8 post-training quantization (PTQ). Proposed 8 × 8 AMs achieved up to 31.41% reduction in power-delay product (PDP) when compared with the state-of-the-art design, with accuracy drops below 1% across all four benchmarks.
Neuromorphic hardware promises large energy savings for spiking neural network (SNN) inference, yet cross-platform deployment remains inefficient. The Neuromorphic Intermediate Representation (NIR) provides interoperability across seven simulators and four hardware platforms but performs no optimization. We present NeuroCompile, an NIR-level optimization and code-generation framework for the event-driven and sparse nature of SNN workloads. It applies three passes—Spike-Rate-Aware Operator Fusion (SRAF), Temporal Tiling (TT), and Platform-Adaptive Quantization Scheduling (PAQS)—and emits a prototype Lava back-end for Intel Loihi 2. Each pass is formalized with explicit linear-time algorithms. We evaluate the framework on five trained SNN architectures and a 49.7M-parameter Meta-SpikeFormer-V2-scale NIR graph targeting Loihi 2 and SpiNNaker2. All reported energy and latency numbers are predictions of an analytical cost model rather than hardware or cycle-accurate-simulator measurements. Under this model, NeuroCompile is estimated to reduce energy by 73%–98% on Loihi 2 and by 47%–50% on SpiNNaker2 relative to a naive NIR deployment baseline; the relative ranking of pass combinations is preserved under ±30% perturbation of every cost-model parameter. PAQS is the dominant pass at the model scales evaluated here, while SRAF and TT are scale-dependent compiler mechanisms whose effect grows as spike-rate or working-set conditions move toward published-hardware limits. Inference-only function-preservation probes on small calibration batches suggest that PAQS-assigned mixed precision is comparable to uniform INT4 on top-1 decision agreement; full-validation-set accuracy on physical Loihi 2 and SpiNNaker2 hardware remains outstanding. To provide independent corroboration beyond the analytical cost model, we add a cross-platform hardware-validation campaign (Section 8.4) that reports live per-inference energy measured on five real estimators: an NVIDIA RTX A6000 workstation GPU with NVML power probing, an NVIDIA Jetson Orin Nano 8 GB with INA3221 VDD_IN rail probing, an NVIDIA Jetson Orin NX 8 GB with the same probe, an AMD/Xilinx Kria KV260 with its INA260 VCCINT sensor, and Intel’s official Lava Loihi2SimCfg simulator against Davies et al.’s per-op picojoule figures. Across these auxiliary substrates, mixed-precision execution reduced or approximately preserved energy in most configurations while producing platform-dependent increases of up to 7.4% in several model–platform pairs; the two estimators whose energy model is dominated by weight-arithmetic (A6000 and Loihi2SimCfg) show the largest reductions (57% on the smallest model for the A6000, 50% on all five models for Loihi2SimCfg). We therefore describe these results as an auxiliary proxy measurement rather than as physical validation on Loihi 2 or SpiNNaker2 hardware. Compilation overhead is below 0.6 ms; the 49.7M-parameter result is a graph-level stress test on an untrained NIR graph and is reported as such.
Today, circuits are used in various safety-critical systems, therefore yielding a high demand for correct and reliable systems. Consequently, a lot of research is conducted to improve both the verifiability and testability of designs and therefore guarantee correctness. In this context, provable computational bounds are crucial to ensure fast verification and test pattern generation. Previous works proved Polynomial Formal Verification (PFV) and polynomial upper bounds for the test set generation for Binary Decision Diagram (BDD) circuits. Later, the verifiability and testability of Kronecker Functional Decision Diagrams (KFDDs) was assessed, as KFDDs can exponentially reduce the required logic. However, both formal verification and test pattern generation are generally exponential problems. While the test pattern generation for KFDD circuits is exponential, it has been shown that their formal verification is linearly bounded and can therefore be conducted efficiently. In this paper, we present a technique to derive circuits from KFDDs, for which a full test set under the Cellular Fault Model (CFM), as well as the Stuck-At Fault Model (SAFM), can be generated within polynomial resources. In addition to the polynomial testability properties, we prove that the resulting circuit remains verifiable within polynomial time and space. In our evaluation, the complete test set generation was up to 50 times faster than the previous exponential method, clearly showcasing the advantages of our polynomial approach.
Physically Unclonable Functions (PUFs) have emerged as a promising hardware-based solution for secure key generation and device authentication, leveraging inherent process variations to produce unique Challenge-Response Pairs (CRPs). Among the various architectures, Arbiter PUFs are particularly attractive due to their simplicity and scalability. However, their resilience against physical attacks remains under-explored. This work presents an extended investigation into the impact of pulsed ElectroMagnetic Fault Injection (EMFI) on a Time Measurement-based Arbiter PUF (TIMA-PUF) implemented on an FPGA. The study initially characterizes the vulnerability to single-pulse injections, demonstrating that a precisely tuned pulse can consistently alter the PUF output. The analysis is further expanded to sequential dual-pulse injections, revealing that the fault impact is often mitigated due to the simultaneous increase in propagation delay across competing paths. To address these vulnerabilities, three distinct countermeasures are proposed and detailed: a Token Monitor, a Glitch Monitor, and a novel Response Monitor. Two specific metrics are introduced to quantitatively evaluate the spatial coverage and detection effectiveness of these protections. Experimental results indicate that the proposed countermeasures offer robust spatial detection and high effectiveness while maintaining a low hardware footprint. This is particularly notable for the response monitor, which requires only 27 Look-Up Tables (LUTs). These findings provide a comprehensive framework for enhancing the fault resilience of TIMA-PUF against advanced EMFI threats. Furthermore, we evaluate the resilience of the proposed TIMA-PUF against temperature variations and demonstrate that it incorporates inherent compensation mechanisms that effectively mitigate thermal effects, resulting in a negligible impact on the generated responses.
Embedded systems have become—with billions of instances—omnipresent in our everyday lives. In addition to resource efficiency and reliability, security is one of their key aspects. Bank cards, access systems, electronic passports, medical equipment, transportation systems, or IoT devices, they all carry sensitive information or need encrypted communication.In this paper, we discuss the history of embedded security. We also summarize the basic problems that are being addressed, such as side-channel attacks, random number generators, and physical unclonable functions. A special chapter is dedicated to the Euromicro conference on Digital System Design, where we summarize the research presented in the track Architectures and Hardware for Security Applications (AHSA) over the past decade. Finally, we provide an outlook on the future directions in security of embedded devices.
Real-time decision-making at the edge requires inference engines that simultaneously achieve high accuracy, low latency, and energy efficiency. Among existing machine learning models, decision tree ensembles, such as those produced by XGBoost (eXtreme Gradient Boosting) and LightGBM (Light Gradient Boosting Machine), remain popular for their interpretability and predictive performance. However, the increasing complexity and size of these ensembles hinder their efficient deployment on resource-constrained hardware platforms. This paper presents a novel AI-to-Hardware co-design framework that jointly optimizes the model structure and the hardware architecture to enable efficient decision-tree inference for edge intelligence. The proposed framework integrates a dedicated decision-tree inference accelerator within a heterogeneous multicore System-on-Chip (SoC). On the algorithmic side, instead of relying on conventional gradient-boosted training, a custom Evolutionary Algorithm (EA) is introduced to evolve compact yet accurate ensembles. This approach significantly reduces model complexity and eliminates the need for extended-precision arithmetic typically required by gradient-based methods. The resulting system supports runtime model configuration, hardware-in-the-loop training, and online learning, enabling adaptive intelligence under dynamic operating conditions. Experimental validation on radar and electronic warfare classification benchmarks shows that the evolved models achieve near-perfect accuracy (99%-100%) with up to 10 & times; fewer trees than state-of-the-art methods. In contrast, the hardware accelerator achieves up to 800 & times; lower inference latency than a softcore RISC-V CPU and 20x hardcore ARM A9 CPU, both serving as baselines. These results demonstrate the advantages of combining evolutionary learning, heterogeneous SoC architectures, and dedicated accelerators within a unified co-design framework, showing its benefits for efficient, reconfigurable, and open hardware platforms for real-world edge Artificial Intelligence (AI) applications.
Functional verification makes up a substantial fraction of the overall effort in modern digital hardware development. As hardware systems grow in size and complexity, verification environments likewise become more challenging to maintain and extend, particularly in collaborative settings where multiple contributors evolve the testbench over time. This motivates the need for a verification methodology that provides a clear structural organization and encourages reuse through modular and composable testbench components.In this paper, we present Liftoff, a first step towards a complete Scala-based verification framework in which we adopt a structured approach to constructing modular, reusable testbenches. The project draws inspiration from the Universal Verification Methodology (UVM). We analyze the fundamental mechanisms by which UVM achieves modularity and reuse, and identify a minimal subset that delivers comparable expressive power while significantly reducing conceptual and implementation complexity. The expressive host language Scala and its surrounding ecosystem, alongside the revised structuring mechanisms, make for a productive verification environment. The resulting framework is a lightweight verification environment for Verilog and Chisel designs in Scala, supporting both simple unit-test-style verification and the construction of more elaborate, UVM-like structured testbench architectures.
The analysis of wafer map patterns is crucial for detecting manufacturing defects in integrated circuits. Although deep neural networks have been used for this task, spiking neural networks (SNNs) offer a more energy-efficient alternative by using spike activations, replacing multiplications with simpler additions. We develop an SNN with ternary spiking neuron model that outputs values of {-1, 0 0, 1} instead of the traditional {0, 1}, to enhance the neuron's information capacity and learning. It also improves the model's control over the influence of each type of spike on the membrane potential, helping to prevent excessive activation and maintain stability by balancing excitatory and inhibitory signals. Using direct spike training with pseudogradients, our model outperforms both binary SNNs and DNNs on the WM-811k wafer benchmark dataset, excelling in identifying critical defect patterns that are underrepresented in the dataset with high accuracy and computational efficiency.
As memory components shrink, their susceptibility to manufacturing defects and non-idealities, involving complex electrical effects, increase. The resulting complexity of the induced fault mechanisms and the tests capable of detecting them also increase. To address this increasing complexity, new memory test paradigms are investigated, such as memory functional and structural testing in digital test environments, leveraging powerful test tools such as Fault Simulator (FS) or Automatic Test Pattern Generator (ATPG). While previous works have demonstrated the feasibility of the digital test approach for Static Random Access Memory (SRAM) testing, the complexity of the memory faults that could be addressed was limited. This work proposes the Hardware Context Monitoring (HCM) digital test methodology, that allows high complexity dynamic memory faults to be covered in digital test environments. Several HCM test modules are presented in this work to demonstrate the HCM test methodology capability to address dynamic Read Destructive Faults (dRDF) and resistive Address Decoder Open Faults (r-ADOF).
This research article focuses on the design and optimization of ripple carry adders and carry-save adders in the Quantum-dot Cellular Automata (QCA) framework, offering a compelling alternative to traditional microelectronic technology, providing novel features like enhanced power efficiency, speed, and density, with the capability to surpass CMOS limitations, using quantum dots for binary data representation. This nanotechnology showcases distinct implementations of efficient 2-bit, 4-bit, 8-bit, and 16-bit RCA circuits, as well as CSA circuit layouts, using coplanar crossovers generated with QCADesigner 2.0.3 in the QCA nanocomputing circuitry. The suggested 8-bit RCA achieves significant reductions of 86% in cell count, 82% in area, 71% in latency, and 98% in area-delay cost, while the 16-bit RCA shows reductions of 69%, 7%, 5%, and 17%, respectively. The proposed 4-bit CSA design reduces the cell count by 63%, the area by 64%, the latency by 14%, the area-delay cost by 85%, and the QCA-specific cost by 90%. Thereby, the novel 8-bit and 16-bit CSA circuit layouts are well-implemented and analyzed. The comprehensive energy dissipation analyses using the QCADesigner-E tool further underscore the potential of the proposed QCA layouts to deliver high-performance, energy-efficient digital arithmetic nanocircuits.
Post-quantum cryptography and privacy-preserving technologies are expected to play a central role in future secure communication systems. Lattice-based PQC schemes such as ML-KEM (CRYSTALS-Kyber) and ML-DSA (CRYSTALS-Dilithium) rely heavily on large-degree polynomial arithmetic, making the Number Theoretic Transform (NTT) a key computational primitive. Although existing hardware accelerators exploit parallelism and pipelining to support both NTT and INTT, their efficiency is often limited by the overhead of modular reduction and correction steps, inverse-transform scaling operations, and suboptimal FPGA implementations. This work addresses these limitations by proposing parallel iterative NTT/INTT accelerators based on optimized unified butterfly units. We introduce a novel redundant number representation that eliminates conditional corrections for both Montgomery modulo multiplication and combined subtract–multiply operations, and integrate inverse-transform scaling into existing arithmetic hardware to avoid dedicated scaling units. Furthermore, we design hierarchical Montgomery multipliers that map efficiently onto FPGA DSP resources, reducing hardware cost while enabling high operating frequencies. FPGA-based experimental results demonstrate higher clock frequencies, reduced execution times, and competitive resource utilization, supporting efficient NTT acceleration for PQC and related privacy-preserving applications.
The Portable Test and Stimulus Standard (PSS) is an emerging standard enabling higher abstraction for simulation-based verification through graph-based stimulus generation, promoting modular reuse. However, achieving vertical reuse-integrating block-level PSS models into top-level ones-remains a significant challenge due to the manual effort required. This article introduces static analysis as an essential phase in automating vertical reuse. It applies data and control flow analyses combined with a Satisfiability Modulo Theories solver to trace signal paths from the top-level design to its submodules. Experimental validation demonstrates the applicability of the approach on the execution stage of a real-world RISC-V processor design. Its scalability and efficiency are further evaluated using a configurable benchmark with varying design sizes and hierarchy levels, while additional open-source designs are used to provide contextual support. The findings show that static analysis provides sufficient information about interconnections and dependencies in complex top-level designs to determine the connections necessary for automating the vertical reuse of PSS models.
In safety-critical applications such as autonomous driving and robotics, the reliability of Deep Neural Networks (DNNs) performing video semantic segmentation is paramount. However, detecting hardware-induced faults in these complex tasks remains a challenge. State-of-the-art methods often evaluate fault criticality using overly conservative metrics like mean Intersection over Union (IoU) or Pixel Accuracy (PA). Furthermore, for online detection, they typically require invasive white-box access to internal states and miss transient faults by analyzing only single frames. To address these limitations, this work proposes a novel, unsupervised Spatio-Temporal Fault Detection framework. The proposed Single Frame and Temporal Consistency (SFTC) methodology leverages a dual-phase strategy: Single Frame Consistency (SFC), which evaluates geometric features (Area, Position, Symmetry, Shape) to identify structural degradations within single frames, and a Temporal Consistency (TC), which monitors frame-to-frame dynamics to detect transient faults that violate structural and visual continuity. To validate this approach, we present an extension of the Faulty Output Dataset (FOD), now covering both outdoor automotive scenarios (Fast-SCNN on Cityscapes) and indoor robotic environments (ESANet on NYU Depth V2). Experimental results for both permanent and transient faults demonstrate that the synergy between spatial and temporal monitoring significantly enhances reliability, achieving a detection rate increase of up to 9.14% compared to the state-of-the-art performance, by operating in a fully black-box way.
Effective real-time cardiac monitoring requires hardware capable of analyzing complex physiological signals without draining the battery or causing critical delays. While Convolutional Neural Networks (CNNs) are highly accurate at diagnosing heart conditions by fusing Electrocardiogram (ECG) and Phonocardiogram (PCG) data, deploying these models on wearable edge devices often hits the Von Neumann memory bottleneck. In standard processors, constantly shuffling data back and forth creates unacceptable power and latency overhead. To solve this, the mlCardioGuard architecture is introduced, a custom, ultra-low-power Application-Specific Integrated Circuit (ASIC) built expressly for multimodal cardiac inference. Instead of using traditional sequential time-multiplexing, the proposed design features a dual-stream, fully pipelined 1D-CNN datapath that handles ECG and PCG signals simultaneously. The memory architecture is also completely rethought to cut energy costs. By using shift-register-based feature buffering and mapping INT8 weights directly into on-chip ROM, this memory-independent dataflow entirely eliminates the need for power-hungry off-chip and on-chip SRAM accesses. The hardware was validated on a Xilinx Kintex-7 FPGA and the ASIC was synthesized using a commercial 90 nm CMOS standard-cell library via Cadence Genus. The resulting layout is incredibly compact, using just 3106 logic cells across a 35,803.64 mu m2 footprint. Running at a 100 MHz clock, the pipeline achieves a deterministic inference latency of exactly 5 clock cycles while drawing only 2.17 mW of total power (2.00 mW dynamic, 0.16 mW leakage). By structurally eliminating the memory-fetch bottleneck, this architecture drastically improves throughput and energy efficiency compared to existing biomedical accelerators, making it a highly practical engine for next-generation wearable health monitors.
Sail is a language for defining the architectural behavior specification of instruction set architecture (ISA) of processors, and it has been chosen to serve as a formal specification of the RISC-V architecture. Consequently, Sail compiler can automatically generate emulator code in C or OCaml from the Sail RISC-V model. However, the generated sequential emulator would not be a good performance evaluation tool, as it is basically a functional simulator that does not simulate the pipelined execution of RISC-V instructions at the cycle level. This paper proposes an enhancement by incorporating a pipeline module into the Sail system so that the Sail compiler could parse the Sail RISC-V model and then generate a cycle-accurate simulator for a 5-stage pipelined RISC-V processor. Furthermore, the original Sail simulator does not support system calls, and consequently cannot properly execute real-world benchmark programs. This paper adopts another enhancement into the Sail RISC-V simulator by supplementing a system call handler. Preliminary performance evaluation will be conducted using MiBench and PolyBench benchmark suites.
