Homogeneous Synchronous DataFlow Graphs (HSDFGs) have become a popular method for analysing the performance of manufacturing systems. Manufacturing tasks, modelled by actor firings in an HSDFG, are bounded by their earliest possible starting times, determined by the completion of preceding tasks. Taking into account these lower bounds, an HSDFG represents different possible task schedules for these tasks, namely any actor firing scheme that satisfies these lower bounds. However, in some cases, tasks in a manufacturing system must be completed before a deadline, which introduces an upper bound. Additionally, the relative start times between tasks may need to adhere to a lower bound. Such lower and upper bounds are not naturally supported by classical HSDFGs. In such cases, an HSDFG cannot represent all relevant aspects of the behaviour of a manufacturing system. This article extends the HSDFG model to support the specification of lower-bound and upper-bound constraints on timing differences between actor-firing starts and completions. The paper then presents a new method for transforming extended HSDFGs into a (max, +) linear system in the form of its state-space matrices. This system can be used to synthesize a task schedule that adheres to the specified lower and upper bounds while achieving the earliest possible execution times, optimizing throughput or makespan. We illustrate the necessity for specifying lower and upper bounds, and the application of our techniques, with a manufacturing system case study.
Direct Access (DA) in Disaggregated Memory (DM) is a promising solution that meets the high-performance requirements of AI applications. However, it lacks effective support for metadata management, making metadata operations the major bottleneck. To address this, we propose Lemonade, a learning-based heterogeneous metadata offloading for disaggregated memory. Lemonade splits the metadata into highly regular and irregular ones, thus offloading the former into the client to avoid remote queries and enabling request redirection in the SmartNIC for the latter to ensure cost-effective correction and updates. Evaluations under microbenchmark and YCSB workloads indicate that Lemonade reduces latency by 72.8% and achieves a 1.43× increase in throughput compared to the state-of-the-art systems.
In key-value store systems, data security is often prioritized through compression and encryption of stored key-value pairs, ensuring protection against unauthorized access and breaches. However, these security measures introduce significant performance overheads, particularly during read operations, due to the need for decryption and decompression of data packs. This overhead is exacerbated in log-structured merge-tree (LSM-tree) based systems interfaced with NAND flash memory, where read amplification—caused by accessing entire compressed and encrypted units for a small subset of data—degrades performance. To address this challenge, we propose ReLoaD (Repacking Locality Data), a novel locality-based strategy designed to optimize read performance in encrypted key-value systems without compromising security or compression efficiency. ReLoaD leverages dynamic access pattern analysis to reorganize frequently co-accessed key-value pairs into contiguous storage packs, reducing the frequency of costly decryption and decompression operations. By introducing lightweight in-memory data structures—such as the PackInfo and Remapthl mapping tables—and innovative mechanisms like the locality-aware compactor and reloading repacker, ReLoaD enhances data locality within packs, minimizes I/O overhead, and increases the pack read ratio. Experimental evaluations using real-world workloads from X (formerly known as Twitter) and IBM, executed on the RocksDB platform, demonstrate that ReLoaD achieves up to a 38% improvement in read latency compared to state-of-the-art solutions like TinyEnc, while maintaining minimal impact on write performance. With a memory footprint of less than 3 MB, ReLoaD offers a scalable and practical approach to balancing security and performance, making it well-suited for modern secure storage systems deployed in resource-constrained environments.
The legacy block interface for I/O benefits from data locality but faces challenges with I/O amplification due to the frequent small read-write operations common in most applications. Dual-Interface SSDs, which integrate block-interface Flash memory with byte-addressable memory, create opportunities for application redesign by reducing unnecessary read-write amplification on storage devices. However, current Dual-Interface SSD hardware remains limited in terms of size and functionality. Existing software designs for Dual-Interface SSDs often use the byte-addressable space as sequential logs with basic batch reclamation. While this space allows random access, and batch reclamation introduces significant tail latency caused by excessive read and write-back operations. To fully exploit the potential of Dual-Interface SSDs, we have developed a prototype on a hardware-software configurable platform. This publicly accessible Dual-Interface SSD offers realistic and optimized performance, overcoming the size and functionality limitations of previous designs. In addition, we demonstrate the ability of Dual-Interface SSDs to reduce write amplification in a traditional Copy-on-Write B-Tree data store. By employing two key techniques–Tree Pointer Relocation, which decouples indirection from the tree structure, and Tree Node Accommodation, which enables small-sized key-value pair updates to be processed directly in the byte-addressable space–we significantly improve the efficiency of storage operations. Our evaluation reveals that these techniques, when applied to Dual-Interface SSDs, achieve performance gains of 30.5% and 52.5% compared with a CoW B-Tree operating on traditional block-interface SSDs.
Graph Neural Networks (GNNs) are made up of multiple layers, with each layer comprising of different compute kernels involving weight vectors and adjacency matrices of input graph dataset. These layers exhibit varying features such as sparsity, storage requirement, and impact on predictive accuracy. Non-volatile memory (NVM)-based 3D Processing-In-Memory (PIM) architectures offer a promising approach to accelerate GNN inferencing. However, NVM device-based crossbars suffer from various non-idealities that affect the overall predictive accuracy. In this work, we consider the problem of finding a suitable mapping of GNN layers to PIM-based processing elements (PEs) in a 3D manycore architecture such that the impact of crossbar non-idealities on predictive accuracy is minimized. We develop a framework called GINA, which leverages low-cost, approximate Hessian-based methodology to automatically determine the GNN layers that are critical for accuracy and find a suitable GNN layer to PE mapping. To tackle non-idealities and to exploit sparsity at the crossbar level, a subset of the full crossbar is activated in a cycle, referred to as Operation Unit (OU). However, OU configurations vary with the above-mentioned GNN layer features, time-dependent conductance drift, and input graph dataset. GINA learns to optimize the OU configuration for unseen datasets as a function of GNN layer features and time-dependent conductance drift. Our experimental results demonstrate that GINA-enabled 3D PIM architecture reduces the latency and energy by 7.4 imes and 13 imes on an average, respectively, compared to state-of-the-art PIM architectures without compromising the predictive accuracy. Finally, we demonstrate the applicability of GINA to Convolutional Neural Networks (CNNs) and Vision Transformers.
Torus is a symmetric Network-on-Chip (NoC) topology with uniform node degree providing very high path diversity between a pair of source and destination. Moreover, the Wraparound Channels (WCs) in the torus can significantly reduce the hop count, thereby reducing overall communication latency. However, the WCs also create cyclic paths that may lead to a NoC deadlock. As a consequence, very few deadlock-free routing algorithms for torus-based NoC exist that do not have significant implementation overhead. Furthermore, the existing routing algorithms do not unlock the full potential of the torus-based NoC topology. In this work, we present a formal modeling-based technique for developing deadlock-free routing algorithms for torus-based NoC. This method systematically combines routing algorithms of mesh with WCs of torus to develop deadlock-free routing algorithms for torus. Using the proposed technique, we develop three novel routing algorithms and verify their deadlock-freedom using Directional Dependency Graph (DDG). We then evaluate the proposed routing algorithms using both synthetic and real traffic patterns. The primary objective of this work is to present a technique that can generate multiple routing algorithms and not the single best routing algorithm. Hence, we do not claim that the three proposed algorithms are the best-performing ones. Nevertheless, we show that they can save hop counts by more than 10% and latency by 8% compared to the competitive methods. The performance of our algorithms is comparable even with state-of-the-art Table-based rout- ing and deadlock recovery-based technique.
For smart mobile devices such as smartphones, daily usage involves a large set of apps and frequent app switching. App-switching latency is highly perceptible to users and is heavily subject to swap efficiency. Hybrid swapping, which combines compressed ramdisk (zRAM) and flash storage, is becoming increasingly popular in modern smartphones. However, existing approaches allocate these heterogeneous swap resources without app-level differentiation, resulting in suboptimal swap efficiency. To address this issue, we propose an integrated approach to hybrid swap based on app-level differentiation, involving three key strategies: app-aware page admission, which prioritizes hot-app pages for zRAM while directing cold-app pages to flash swap; app-aware page migration, which applies per-app criteria to identify and migrate dormant pages from zRAM to flash swap; and app-aware flash swap, which exploits swap space isolation and enhanced prefetching to mitigate flash-induced latency during app switching. Swap space isolation preserves the correlation of sequentially evicted pages from the same app, while our new prefetcher exploits dual correlations in eviction sequences and virtual addresses through per-app prefetch windows. Experimental results show that our approach reduces app-switching latency by up to 63% compared with existing methods.
Cyber-physical systems (CPSs) often contain components whose internal design is unknown, making their verification challenging. Although black-box checking (BBC)—an automated black-box testing method that combines automata learning and model checking—can detect unsafe behaviors without requiring a complete model, it becomes computationally expensive for large or infinite-state systems. To address this problem, we propose a specification-guided abstraction that identifies and merges states in the system’s state space if they are equivalent under the verified specifications. Building on this abstraction, we develop an algorithm that directly learns the resulting abstract Mealy machine, thereby bypassing the need to learn the full system behavior first. We then integrate the new learning procedure with model checking to obtain an enhanced BBC framework that efficiently handles large or infinite-state systems, particularly when verifying multiple properties. Our empirical evaluation demonstrates that specification-guided abstraction improves detection and efficiency in uncovering unsafe behaviors in CPSs.
The rapid adoption of Electric Vehicles (EVs), driven by stringent environmental regulations and rising fuel costs, is reshaping the landscape of Vehicle Routing Problems (VRP). This shift has led to the Electric Vehicle Routing Problem (EVRP), which incorporates EV-specific operational constraints such as limited driving range, energy consumption, recharging strategies, and detour-related charging costs. The challenge becomes even more critical in modern mixed fleets, where Electric and Internal Combustion Engine Vehicles (ICEVs) coexist and must be co-routed efficiently. A widely adopted two-step strategy first uses Capacitated VRP (CVRP) algorithms to generate energy-oblivious routes, then makes EV routes energy-feasible via charging station insertion. While VRP and CVRP are extensively studied, methods for efficiently ensuring energy feasibility for EVs on fixed routes remain limited. This article introduces the Fixed Route Vehicle Charging Problem with Discrete Partial Charging (FRVCP-DPC), extending FRVCP by allowing partial recharging up to predefined discrete levels. We develop a scalable optimal Dynamic Programming algorithm, Best Energy Feasible Route Generator (BEFRG), to select detour points, charging stations, and charge levels that minimize total route time while maintaining energy feasibility. To evaluate BEFRG in dynamic traffic conditions, we introduce EFRGen, a traffic-aware EVRP simulator built on Simulation of Urban Mobility (SUMO) and OpenStreetMap (OSM). Experiments on the Montoya benchmark—spanning 120 instances with up to 320 demand points and 38 charging stations—show that BEFRG computes optimal solutions for all cases within one minute.
As multicore hardware becomes increasingly prevalent in real-time embedded systems, traditional scheduling techniques that assume a single worst-case execution time for each task are no longer adequate, as they fail to account for the impact of shared resources—such as cache and memory bandwidth—on execution time. When tasks execute concurrently on different cores, their execution times can vary substantially with their allocated resources. Moreover, the instruction rate of a task during a job execution varies with time, and this variation pattern differs across tasks. Therefore, to improve performance it is crucial to incorporate the relationship between the resource budget allocated to each task and its time-varying instruction rate in task modeling, resource allocation, and scheduling algorithm design. Yet, no prior work has considered the fine-grained dynamic resource allocation and scheduling problems jointly while also providing hard real-time guarantees. In this article, we introduce a resource-dependent multi-phase timing model that captures the time-varying instruction rates of a task under different resource allocations and that enables worst-case analysis under dynamic allocation. We present a method for constructing estimates of such a model based on task execution profiles, which can be obtained through measurements. We then present Rasco, a co-design technique for multicore resource allocation and scheduling of real-time DAG applications with end-to-end deadlines. Rasco leverages the resource-dependent multi-phase model of each task to simultaneously allocate resources at a fine granularity and assign task deadlines. This approach maximizes execution progress under resource constraints while providing hard real-time schedulability guarantees. Our evaluation shows that Rasco substantially enhances schedulability and reduces end-to-end latency compared to the state of the art.
Directed Acyclic Graph (DAG) models are extensively utilized across fields such as automotive, wireless communication, and deep learning, to capture the inherent functional dependencies. Topology of DAG has a significant impact on the performance of scheduling and resource management algorithms applied to it. Hence, it is imperative to generate all DAG topologies within the parameter ranges pertinent to an application domain, for impartial evaluation of such algorithms. Unfortunately, the existing DAG generators that are capable of offering full topology coverage have limited scalability and controllable parameters. This work reports open-source FT-DAG, an efficient and formally verified full-topology DAG generator that is able to control all major parameters, including the longest length, shortest length, width, jump layer, jump level, in-degree, out-degree, shape value as well as the number of nodes and edges. Experiments show that when the number of nodes is larger than 20, FT-DAG provides at least two orders of magnitude speedup compared to the state of the art and more orders to other generators. FT-DAG scales to 100 nodes in a typical industrial case study within hours.
Certification on a component level is highly beneficial in industrial automation because it allows for independent verification and updates without compromising the reliability of the overall system. Containerization technologies naturally address this demand by providing isolation between software modules. In particular, WebAssembly-based (Wasm) containerization is gaining popularity in industrial automation due to its inherent advantages, including cross-platform interoperability and secure execution of untrusted third-party code. However, Wasm’s strict sandboxing poses a significant limitation as it severely limits interaction with hardware devices, making it difficult to interface with sensors and actuators. This is a substantial barrier to adoption in industrial automation, where real-time and low-level hardware interactions are critical. To address this challenge, we present Wasm-IO, a framework designed to facilitate peripheral Input/Output (I/O) operations within WebAssembly (Wasm) containers. Wasm-IO allows the development of isolated device drivers in Wasm, explicitly moving hardware interaction to the container level. Our architectural approach facilitates containers with hardware interaction to be independently certified, updated, and maintained without adversely affecting each other. This article elucidates foundational methodologies and practical implementations supporting synchronous and asynchronous I/O operations and methods for embedding platform-independent peripheral configurations within Wasm binaries. Additionally, we present an extended priority model enabling interrupt handling in Wasm while maintaining temporal isolation. Our evaluation demonstrates that Wasm-IO significantly reduces latency and overhead compared to existing methods and traditional user-level driver implementations, effectively addressing certification and functional requirements critical to industrial automation systems.
Modern critical cyber-physical systems such as autonomous vehicles, drones, and real-time medical monitoring, demand not only intensive data processing but also stringent adherence to real-time performance constraints. These applications often involve continuous or sequential data streams (e.g., images, videos, and sensor readings), which require frequent memory accesses. Despite advancements in processing power, huge variable interference delay is incurred within the Dynamic Random Access Memory (DRAM) accesses. However, achieving a tight bound of memory latency remains a significant challenge, yet it is essential for ensuring safe and predictable execution of these critical tasks. To address this bottleneck, we propose InterStellarRT, a novel hardware/software harmony methodology that provides data-aware optimizations across the entire memory hierarchy. Leveraging a software layer that communicates data access patterns to the memory controller, InterStellarRT achieves significant reductions in memory access times, ensuring tightly bounded and predictable times. We perform the theoretical analysis of the memory latency bound. Then, we prove that InterStellarRT provides remarkable tighter memory latency bound for in-isolation and interference latencies compared to the state-of-the-art real-time systems based on the Commercial-Off-The-Shelf (COTS) Double Data Rate 4 (DDR4) memory devices and is also applicable to DDR5. We evaluate InterStellarRT on a RISC-V-based quad-core system on GEM5 and DDR4 in Ramulator. Analyzing benchmark results from Polybench, LAPACK, Phoenix, and HPCG Suites, InterStellarRT achieves a 3.8× tighter average bound for in-isolation memory latency and 13.5× for interference latency under affine workloads, while for mixed-affinity workloads, the bounds are 2.15× and 4×, respectively. Moreover, InterStellarRT achieves average 1.72× end-to-end speedup, and 1.9× bandwidth improvement, and 14% DRAM energy reduction against the baseline.
NAND-flash-based solid-state drives (SSDs) are under constant pressure to deliver higher storage density while minimizing power and performance overhead. As the number of bits stored per NAND flash cell has scaled from single-level cells (SLC) to triple-level cells (TLC) and soon to penta-level cells (PLC), the reduced voltage margins between cell states challenge data reliability, requiring stronger decoding techniques. To maintain reliability and correct error data bits, low-density parity-check (LDPC) codes are widely deployed on these high-density devices and can operate in two modes: hard decoding, which uses threshold-based bit decisions and is relatively power-efficient, and soft decoding, which leverages additional reliability information but imposes higher computational and energy costs. In practice, NAND flash controllers initiate soft decoding when hard decoding fails, thereby preserving data integrity at the expense of latency and power overhead. Current approaches employ read-retry tables to adjust reference voltages and maximize hard decoding success rates; however, such tables cannot fully address diverse bit-error patterns, often unnecessarily invoking soft decoding and incurring significant performance overhead. To overcome this limitation, we propose a novel LDPC-syndrome-based loss function that adaptively adjusts multidimensional reference voltages, significantly reducing unnecessary soft decoding triggers without relying on predetermined read-retry tables or iterative voltage adjustments. Experimental results demonstrate that our proposed loss function effectively reduces the soft decoding trigger rate and the number of page reads, substantially minimizing the performance and power costs associated with soft decoding.
By interfacing computing logic directly to the DRAM banks, bank-level Compute-near-Memory (CnM) architectures promise to mitigate the bottleneck at the memory interconnect. While this computation paradigm heavily reduces the energy requirements for data movement across the system, current solutions fail to co-optimize hardware and software to further increase efficiency. Instead, in this manuscript, we present SideDRAM, a co-designed bank-level CnM architecture to enable massively parallel and energy-efficient computations near DRAM. In contrast with past solutions, we support flexible data typing and heterogeneous quantization, relying on the robustness of workloads to employ small bitwidths, and enable a row-wide access to the banks to exploit parallelism and spatial locality. As a result, SideDRAM integrates (1) software-defined SIMD (SoftSIMD) datapaths, supporting low-energy computing with flexible precision, (2) an interface to the banks based on very wide registers (VWRs), enabling asymmetric data access to both utilize the full DRAM bank bandwidth and leverage data locality at the datapath, and (3) a low-overhead distributed control plane, allowing the efficient handling of variable data typing. We benchmark SideDRAM as a near-DRAM solution by analyzing the area, performance, and energy consumption of an HBM2 CnM channel executing heterogeneously quantized machine learning models. The results show that, compared to the state-of-the-art FIMDRAM design, energy improvements of up to 67% are achieved when a DeiT-S inference is executed with a batch size of 16 under the same area constraints, resulting in energy-delay-area product (EDAP) savings that reach 83%. When comparing to a massively parallel mixed-signal CnM solution, SideDRAM consistently obtains similar performance and better energy efficiency results (geomean of 15× improvement across workloads) at a lower area overhead.
Contention in shared caches caused by concurrently executing applications can lead to overall performance degradation in multiprocessor systems-on-chip (MPSoCs). To address this issue, various shared cache arbitration techniques have been proposed to manage cache bandwidth contention. These techniques focus on enhancing overall system performance; however, this optimization often comes at the expense of system fairness, leading to some applications experiencing disproportionate slowdowns, or, in the worst case, starvation. Therefore, an effective shared cache bandwidth management policy is needed to optimize performance while ensuring fairness across applications. We propose FARRE, a novel fairness aware request-response arbitration technique for shared caches. FARRE is designed to optimize performance while attempting to maintain a user-defined fairness threshold. We evaluate its effectiveness through extensive simulations including comparisons against state-of-the-art arbitration schemes. The results show that FARRE is able to maintain or exceed the input fairness thresholds, and improves system performance over standard fair scheduling policies such as round-robin; the performance improvement is 14% for lower fairness thresholds such as 0.5, and could even gain 5% performance for aggressive thresholds such as 0.9. Additionally, compared to the best performance optimization techniques, FARRE achieves 81% higher fairness.
Pipelining deep neural networks (DNNs) across multiple Edge Tensor Processing Units (TPUs) can enhance on-device performance by increasing the capacity for DNN parameters caching and enabling pipeline parallelism. Effective deployment on pipelined Edge TPUs requires a partitioning tool to divide the DNN into segments, each assigned to a different Edge TPU in the pipeline. Achieving balanced workload distribution across these segments is crucial for optimal timing performance. However, workload balancing across Edge TPUs is challenging, as DNN execution time is influenced by proprietary hardware architecture and compiler internals, forming a black-box function inaccessible to partitioning tools. To address this challenge, this article introduces SAPar, a new surrogate-assisted DNN partitioner that integrates a neighborhood search engine with a surrogate-assisted evaluator for effective and efficient DNN partitioning. The neighborhood search engine systematically explores the decision space, guided by knowledge obtained from empirical insights and neighborhood evaluation feedback provided by the surrogate-assisted evaluator. The evaluator cooperatively applies an accurate yet time-consuming latency profiler and an efficient graph transformer-based surrogate model, achieving both precision and scalability. Experiments on real Edge TPU hardware demonstrate that SAPar achieves significantly better pipeline performance than Google’s current profiling-based partitioner with an 8.82× to 110× speedup in partitioning time. Moreover, SAPar reduces the bottleneck latency by 8.93% to 44.15% across five classic DNN models compared with a state-of-the-art reinforcement learning-based partitioner.
Real-time scheduling of multiple control tasks in a weakly hard setting is an emerging research direction, as it offers a more flexible and feasible environment for task scheduling. This is especially pertinent for resource-constrained embedded applications where tasks are allowed to miss a few deadlines for prudent sharing of computational resources. However, a control task missing its deadline could result in the system being unsafe or unstable. A significant amount of research efforts have been reported in the literature addressing the schedulability of control tasks while preserving the stability or safety. However, all of them focus on a stable schedule or a safe schedule, but not both the safety and stability aspects together. In this work, we ensure both control stability and control safety to generate a safe and stable schedule for a weakly hard task system. In particular, we gradually endorse stability, safety, and schedulability, where we first synthesize a weakly hard constraint that preserves the desired stability of each control task. Next, we correlate stability with control safety and establish some mathematical results that guarantee control safety for an unbounded time horizon, unlike the existing methods. Finally, by leveraging Satisfiability Modulo Theories (SMT), we synthesize the schedule that ensures control stability and safety while minimizing the worst-case response time of all the tasks, in a time-efficient way. To our knowledge, this is the first work to address stability, safety, and schedulability together for weakly hard control task systems. We validate our method through extensive experiments using standard automotive benchmarks. In addition, we demonstrate the efficiency of the proposed method in comparison with some of the state-of-the-art techniques, as well as highlight its scalability, thereby establishing its applicability in real-world scenarios.
In large-scale cloud data centers and distributed storage systems, erasure coding is usually employed to enhance data availability and storage efficiency. However, with the explosive growth of data volume and the continuous expansion of storage system scale, traditional erasure coding techniques face significant challenges in handling single-disk failures. These challenges are primarily reflected in low data recovery efficiency and imbalanced system load distribution, which ultimately result in excessive I/O load and network bandwidth consumption, severely limiting the overall performance of the system. To address these issues, this article proposes a load-balanced data repair algorithm for single disk failures in erasure coded storage systems, called MNCR (Multi-Node Cooperative Repair). This algorithm improves data recovery efficiency in single-disk failure scenarios by minimizing data reading and inter-disk data transmission, using a cooperative repair strategy among disks. In addition, the algorithm designs a dynamic load balancing mechanism, which effectively resolves the issue of imbalanced data load distribution among disks during the repair process, thus avoiding performance bottlenecks caused by overloaded disks. Experimental results show that the MNCR algorithm significantly outperforms traditional methods in terms of repair efficiency and load balancing, providing an effective solution for single disk failure recoveries in erasure coding based large-scale storage systems.
High-density NAND flash has revolutionized the storage ecosystem because of its rapidly decreasing per-bit costs and unprecedented capacities. However, the inherent large block size of modern high-density NAND flash inevitably aggravates the reclamation latency (i.e., the time required to reclaim the storage space occupied by the obsolete data), which subsequently prolongs the tail latency of flash-based storage devices. Inspired by the “erase duality” from the emerging bit-alterable NAND flash, this article proposes a reclamation latency suppressed (RLS) space management design to synergize the strengths of both block-level erase and page-level erase. Taking into account the data update frequency during runtime, RLS enables proactive adjustment of the dual-granularity erase. Moreover, RLS tightly couples the data cluster allocation strategy with a novel dual-granularity space reclamation design, thereby alleviating the reclamation latency. We extensively examine the benefits of RLS with real-world workloads. Our evaluation results reveal that, with the suppressed space reclamation latency, RLS achieves up to 37.51% improvement for both write and read tail latency (latency at the 99.9th percentile) compared with the state-of-the-art approaches.
