Debugging hardware designs presents unique and significant challenges compared to software debugging. Software simulators often fail to uncover design issues arising from physical constraints or incorrect elaboration. Traditional hardware debugging tools typically lack flexibility, ease of use, and robust real-time interaction, slowing down the development and potentially compromising security. We present HWDBG which eases hardware debugging by introducing software debugging concepts. Unlike existing approaches, HWDBG allows stepping through the hardware design cycle-by-cycle, visualizing waveforms, and inspecting values (e.g., like a logical analyzer). Users can script both passive and active debugging, modifying signals in real time. Furthermore, it has the potential for reverse engineering and chip fuzzing by injecting random signals to test functionality under different conditions. A key insight allowing HWDBG to achieve these goals is that, unlike existing approaches, it can be synthesized as an FPGA, directly interacting with the device under test in real time. We provide an open-source prototype.
Transformer-based models have emerged as a powerful solution for network traffic classification, achieving high accuracy by autonomously learning patterns in raw traffic data. However, their high computational costs make real-time deployment impractical. In contrast, industry-proven tools like Snort and Suricata offer efficient network analysis but rely on manually crafted signatures, resulting in slower updates and limited adaptability to emerging threats. In this work, we propose a cascading model that leverages the strengths of both approaches. During training, a transformer-based model learns traffic patterns, which are then extracted using SHAP analysis to enhance the knowledge base of a signature-based IDS. In deployment, the IDS handles routine classifications, while only complex cases are escalated to the transformer model. Our experiments combining the analysis of ET-BERT with Snort demonstrate a four-fold performance improvement over running only ET-BERT without compromising false positive or false negative rates.
As the Internet of Things (IoT) ecosystem continues to expand, ensuring robust wireless communication in the face of radio jamming attacks has become a critical concern. This paper presents a comprehensive case study on improving IoT resilience to radio jamming using the Thread protocol within a controlled testbed environment. We investigate the vulnerability of Thread-based IoT networks to constant jamming and implement an effective countermeasure to improve network robustness. Our study focuses on the channel hopping method for countermeasure implementation, demonstrating its effectiveness against jamming attacks through detailed experimental results and analysis. This work underscores how jamming and countermeasure systems can be developed and tested on real hardware, fostering further research in the field of network security. The experimental results provide valuable insights into the efficacy of these strategies in mitigating jamming threats.
The rapid expansion of multi-cloud environments and the growing prevalence of collaborative data ownership present significant challenges in ensuring the verifiable deletion of co-owned data. Current approaches predominantly address individual ownership and often rely on simplistic one-bit result protocols where a deletion command merely outputs success or failure, turning the deletion into a black box without proper verification. This paper tackles the problem of secure processing and verifiable deletion of shared outsourced data in multi-cloud environments. We design a framework that enables a data owner to outsource encrypted data to multiple co-owners, who perform computations directly within their respective cloud providers-ensuring that sensitive data never leaves the cloud. Our system leverages readily available cloud Hardware Security Modules (HSMs) to manage cryptographic keys from generation to controlled destruction-ensuring data remains inaccessible beyond its intended use. Secure Enclaves enforce on-cloud data computation, eliminating local copies and preventing unauthorized exposure. Encrypted data is structured within a fixed storage model, ensuring controlled allocation and strict storage constraints. When data expires or must be deleted to meet regulatory requirements, our framework triggers zero-residual permuted overwriting to remove the data traces irreversibly. Verifiability is achieved at two levels: Bounded Merkle Hash Tree (BMHT) ensures bounded storage and verifiable deletion within each cloud provider. In contrast, Global Merkle Forest (GMF) aggregates BMHT roots across providers, enabling consistent global verification. The data owner maintains a log of these BMHT roots, allowing independent verification of secure deletion across the multi-cloud environment.
The development of reliable authentication schemes is a significant challenge due to vulnerabilities like shoulder-surfing and impersonation attacks. This paper presents a six-month in-lab study (N=30) during which we designed and evaluated a novel two-factor authentication prototype combining Microsoft's Picture Gesture Authentication (PGA) with Electroencephalography (EEG). We aimed to leverage users' unique neural responses during pictorial processing in PGA, in order to train individual AI models that could mitigate impersonation attacks. Additionally, our study examined how users' familiarity with background images affected the accuracy of these models. Results indicated that: a) familiar stimuli enhance cognitive efficiency and authentication accuracy; b) the combination of Wavelet features, Hjorth parameters, and spectral entropy with Support Vector Machines yielded good performance. These findings suggest that EEG-based technology has the potential to improve graphical authentication systems, offering more secure alternatives to traditional methods.
When a website is accessed, a connection is made using HTTPS to ensure that it ends with the website owner and that subsequent data traffic is secured. However, no further assurances can be given to a user. It is therefore a matter of trust that the site is secure and treats the information exchanged faithfully. This puts users at risk of interacting with insecure or even fraudulent systems. With the availability of confidential computing, which makes execution contexts secure from external access and remotely attestable, this situation can be fundamentally improved. In this paper, we propose browser-based site attestation that allows users to validate advanced security properties when accessing a website secured by confidential computing. This includes data handling policies such as the data provided being processed only during the visit and not stored or forwarded. Or informs the user that the accessed site has been audited by a security company and that the audited state is still intact. This is achieved by integrating remote attestation capabilities directly into a commodity browser and enforcing user-managed attestation rules.
Multi-Variant eXecution (MVX) systems are a potent building block for comprehensive memory corruption defenses. They run multiple diversified variants of the same program in parallel, feed them the same inputs, and monitor whether they produce the same outputs. If applied correctly, MVX systems ensure that (i) no single exploit payload can simultaneously compromise all variants and (ii) any exploit causes an observable divergence in the variants' behavior. After repeatedly demonstrating their prowess in detecting control-flow hijacks, MVX systems are naturally keen to extend their protection to data-only attacks, which do not solely focus on corrupting code pointers. However, that would require diversifying the variants' data layout as well, which vastly exacerbates known compatibility issues of existing systems. Due to Address-Sensitive Behavior (ASB), benign programs can behave in dissimilar but functionally equivalent ways depending on memory layout and address values. This causes variants to diverge in ways that are indistinguishable from the effects of an attack to the MVX monitor. In this paper, we explore the practical implications of adopting data diversification in MVX systems. For the first time, we characterize and quantify the issue of ASB across a wide range of real-world software, and find that it is a significant hurdle towards support for data diversification in MVX. To help address this issue, we developed a new variant diffing technique that allows us to recognize and, at times, even neutralize different classes of ASB by locating address-related data in the variants without compiler support.
Rust is a popular programming language with strong memory-safety guarantees, achieved through its ownership and borrowing model. Rust allows a programmer to escape memory safety using explicitly marked unsafe code in order to facilitate integration with existing C/C++ code. Such safe code is not immune to typical memory errors. To avoid such bugs researchers try to provide both static and dynamic analysis tools and incorporate C/C++ hardening techniques for unsafe Rust. However, such analysis is not always trivial as Rust uses multiple intermediate representations (IR), and when lowering a higher level IR to a lower level IR, all information that marks a specific block of code as unsafe is lost. Since the two worlds of Rust, safe and unsafe, are built on different assumptions many analysis tools and techniques can benefit from knowing where the safe context changes to unsafe and vice-versa. In this work, we present a modified Rust compiler (rustc++) that extends the capabilities of the Mid-level Intermediate Representation (MIR) to enable serialization and metadata enhancements. Our framework introduces MIR++, an enhanced MIR representation that embeds metadata identifying safe and unsafe instructions, enabling fine-grained safety tracking throughout the compilation pipeline. Additionally, rustc++ enhances the LLVM-IR representation and produced binaries with metadata allowing LLVM passes and post-compilation analysis tools to distinguish between the safe and unsafe context. Lastly, rustc++ makes preliminary efforts in serializing Rusts MIR to a portable JSON format using the Serde serialization library. Our goal is to allow external tools to work on MIR and its in-memory metadata, without requiring the full compiler pipeline. Modifications of rustc++ maintain compatibility with the existing Rust ecosystem while offering a powerful foundation for future analysis tools.
The rising popularity of Graphics Processing Units (GPUs) has made them an attractive target for attackers looking to steal Intellectual Property (IP) such as ML models or disrupt the operation of heterogeneous computing systems. However, defending against GPU attacks is anything but trivial since the inner workings of these-often proprietary-devices are still poorly understood. Preliminary work demonstrates a worrying similarity to the attack surface of the CPU domain, particularly concerning the memory unsafety of device-side code. We corroborate these worrying findings by constructing the first rigorous experimental analysis of input-triggered, ROP-based exploits entirely within device-side NVIDIA CUDA code. We repurposed known CPU-based code-reuse attack techniques to unlock previously unusable gadgets in this code and demonstrate that the gadget set is Turing-complete, enabling attackers to perform arbitrary computations. We conclude that ROP attacks on GPUs are feasible and more potent than previously thought. Following this discovery, we evaluate the strength of current device-side mitigations, such as stack canaries and Address Space Layout Randomization (ASLR). Given the lack of more powerful protection mechanisms, these basic security measures play a crucial role in GPU security. However, we find them even less secure than their CPU counterparts. Our findings indicate that the GPU domain urgently needs robust protection mechanisms that fit the unique GPU architectures and address the flaws in existing systems.
Microservices are a dominant cloud computing architecture because they enable applications to be built as collections of loosely coupled services. To provide greater observability and control into the resultant distributed system, microservices often use an overlay proxy network called a service mesh. A key advantage of service meshes is their ability to implement zero trust networking by encrypting microservice traffic with mutually authenticated TLS. However, the service mesh control plane-particularly its local certificate authority-becomes a critical point of trust. If compromised, an attacker can issue unauthorized certificates and redirect traffic to impersonating services. In this paper, we introduce our initial work in MAZU, a system designed to eliminate trust in the service mesh control plane by replacing its certificate authority with an unprivileged principal. MAZU leverages recent advances in registration-based encryption and integrates seamlessly with Istio, a widely used service mesh. Our preliminary evaluation, using Fortio macro-benchmarks and Prometheus-assisted micro-benchmarks, shows that MAZU significantly reduces the service mesh's attack surface while adding just 0.17 ms to request latency compared to mTLS-enabled Istio.
Vulnerability prediction is valuable in identifying security issues efficiently, even though it requires the source code of the target software system, which is a restrictive hypothesis. This paper presents an experimental study to predict vulnerabilities in binary code without source code or complex representations of the binary, leveraging the pivotal idea of decompiling the binary file through neural decompilation and predicting vulnerabilities through deep learning on the decompiled source code. The results outperform the state-of-the-art in both neural decompilation and vulnerability prediction, showing that it is possible to identify vulnerable programs with this approach concerning bi-class (vulnerable/non-vulnerable) and multi-class (type of vulnerability) analysis.
The CHERI ISA extension enables modern RISC CPU architectures such as RISC-V to enforce memory safety in C/C++ programs. Recent academic works [2, 7, 15] use CHERI for point solutions like constructing enclaves, verifying C programs, or hardening bytecode interpreters, but since the original construction of the CHERI-BSD OS --- a FreeBSD port leveraging CHERI capabilities, by Cambridge University --- little has been reported on what issues and problems arise when porting an existing operating system to benefit from hardware capabilities. This work distills problematic patterns and their solution from what we believe has been the first successful port of a full Linux system to CHERI hardware. In the interest of reproducibility and possible future CHERI or porting style improvements, we also report on the performance impact of our setup.
Memory safety issues, including buffer overflows and use-after-free errors, continue to pose significant security threats in C/C++ programs, necessitating robust defenses and detection mechanisms. Despite advancements in memory-safe languages like Rust, transitioning legacy codebases often remains impractical, highlighting the need for effective memory safety tools for existing C/C++ code. This paper revisits SoftBound+CETS, an influential combination of two software-only memory safety solutions for C programs, more than a decade after its initial introduction. We present an updated SoftBound+CETS prototype, now compatible with LLVM 12, offering enhanced C language compatibility, interoperability with uninstrumented code, and sub-object bounds checking. Our evaluation, utilizing the SPEC CPU 2017 benchmark suite and the Juliet Test Suite, demonstrates the prototype's improved effectiveness in detecting memory errors with a performance and memory overhead of less than 2x. This is comparable to the widely used but less capable sanitizer ASan. Our future work aims to further reduce overheads and expand compatibility with C++ code and newer LLVM versions. This research highlights the viability of SoftBound+CETS as a comprehensive and practical tool for improving memory safety in legacy C applications, providing a valuable asset for developers and researchers focused on software security.
The advent of inter-connectivity between Industrial Control Systems (ICS) and Information Technology (IT) has greatly enhanced operational efficiency within many Critical National Infrastructure (CNI) sectors, such as energy generation and water treatment. However, prominent industrial network protocols such as Modbus, were designed and implemented without cyber-security considerations, promoting low overheads and real-time communications over digital resilience. Since insecure industrial protocols continue to prevail, considering future protocol implementations and retrofitting security controls to existing exposed environments is critical to mitigate the growing cyber threats that target ICS. In this paper, we aim to address security limitations that are inherent within industrial protocol plain-text transmission, specifically Modbus-TCP. We use Raspberry Pis to represent real resource constrained Modbus devices and evaluate two encryption solutions: 1) Direct on-device encryption and 2) an encrypted SOCKS5 proxy server to facilitate secure communications between Modbus devices. Both methods employ symmetric encryption using stream ciphers and are evaluated for throughput, latency, and Queries Per Second (QPS). Experimental results demonstrate that while on-device encryption provides superior performance compared to the proxy-based solution, it comes at the cost of greater complexity and potential hardware upgrades. Hence, the trade-off between performance and adaptability requires careful consideration.
Virtual Machine Introspection (VMI) is used by sandbox-based dynamic malware detection and analysis frameworks to observe malware samples while staying isolated and stealthy. Sandbox detection and evasion techniques based on hypervisor introspection are becoming less of an issue since running server and workstation environments on hypervisors is becoming standard and high-end sandboxes manipulate virtual clocks to mask VM execution pauses caused by VMI. However, the fake network environment around a sandbox VM offers opportunities similar to hypervisor introspection for malware to evade. Malware can evaluate the discrepancy between observed performances and a real, presumed network environment of infected targets. VMI pauses also cause visible network performance glitches. To solve this issue we propose to extend virtual clock manipulation to synchronize hardware-accelerated virtual machines with a discrete-event network simulator. The experimental evaluation shows that our proposal can counter attempts to infer VMI activity from network timing observations.
Without depending on heavy runtime support, Rust can realize fast machine code that mitigates most of the common attacks associated with memory-corruption and can appear in all unsafe machine code developed using C/C++. Most of the work for producing machine code with security guarantees is carried out at compile-time by the Rust compiler. However, at runtime, there is no mechanism to ensure that the produced security guarantees, as computed at compile-time, are still in place. In this paper, we explore the possibilities of an attacker fabricating Rust binaries so that they are on purpose vulnerable. We show that it is possible to modify automatically, and at large scale, binaries so that certain defences, placed by the Rust compiler, are removed. We introduce a generic problem, and focus on concepts of spatial and temporal safety. Finally, we produce a validator that assesses if all checks ensuring spatial and temporal safety remain intact within a Rust binary, before executing it. Our work is a step towards validating Rust binaries at load time so that security guarantees computed at compile-time are effective at runtime.
Physical Side-Channel Analysis (SCA) is often restricted to less complex devices, such as microcontrollers, as more feature-rich targets, like microprocessor systems, contain possibly multiple sources of systemic noise that influence side-channels and their waveforms non-deterministically in the view of an observer. Thus, locating these waveforms using established waveform matching techniques and subsequent data association becomes impossible. This impedes the application of SCA techniques relying on the relationship of operation waveforms and their processed data. In order to address this issue, this paper presents the CRESTS algorithm, that is capable of locating instances of target operations in larger side-channel traces affected by systemic noise. This enables to extract the waveforms of the relevant operations from the trace and, by maintaining their overall sequence of occurrence, associate them with their corresponding data to then apply established SCA techniques. The effectiveness of our approach is evaluated by applying CRESTS on the widespread XTS-AES algorithm running on a Beaglebone Black System-on-Chip (SoC) target platform.
Data spaces are an emerging concept that allows intermediaries to facilitate data exchange among interested stakeholders. Often, these intermediaries are trusted to filter the relayed data items, e.g., in order to support query-based data access APIs, or to implement access control. In this paper, we explore and compare two approaches for protecting data against illegitimate tampering, balancing the need for data filtering and data integrity protection. We apply our concept in data spaces that serialize data objects using JSON-LD, e.g., data spaces that implement ETSI's NGSI-LD API, and we enable intermediaries to hide segments of the transmitted data, providing at the same time integrity verification proofs for the revealed portions. Both approaches are efficient, with minimal communication and computational overhead.
Analyzing malicious behavior is vital to effectively safeguard computer systems against malware. However, contemporary malware frequently contains evasive behavior, which allows it to hide its malicious intent from analysis. More specifically, if the malware detects it is being executed in an analysis environment, it resorts to evasive routines that exhibit benign behavior. Manually deactivating evasive checks requires significant effort, and is therefore not a scalable technique with regards to the increasing amount of evasive malware. Unfortunately, the existing systems that automatically analyze evasive malware are impractical, computationally inefficient, or incomplete by design. In this paper, we introduce Enviral, an automatic evasive malware analysis framework that proposes a novel method to analyze evasive malware, combining the best elements of existing approaches. We achieve this by applying fuzzing techniques to repeatedly adapt the view of the execution environment, thereby iteratively defeating the evasive checks in the target application. We realize these adaptations by applying mutations to the outcomes of environment queries, which in turn leads to the exploration of multiple execution paths. Our experimental results demonstrate that Enviral can detect and overcome evasive behavior and thereby exposes previously hidden activity in malware. We evaluate our system against a similar framework, and conclude that Enviral can expose 39% more interesting hidden system call activity on average, and achieves productive explorations where previously unseen behavior is discovered in 67% more malware samples.
Unix-and by extension, Linux-traditionally uses a discretionary access control (DAC) paradigm. DAC mechanisms are decentralized by design, which makes it difficult to audit the security of a computer system. Furthermore, Unix systems have the concept of a root user who can bypass any DAC policies in place. These issues led to the development of mandatory access control (MAC) mechanisms, such as AppArmor, Security-Enhanced Linux (SELinux), and eBPF. We compare and contrast the performance differences between two popular MAC mechanisms for the Linux kernel: SELinux and Berkeley Packet Filter (BPF)/kernel runtime security implementation (KRSI). We demonstrate that BPF policies offer superior performance, have greater expressive power, and are easier to implement than comparable SELinux policies. Our results suggest that BPF/KRSI is the leading MAC mechanism for Linux systems.
