This study presents a comprehensive investigation on the properties of negative capacitance field-effect transistors (NCFETs) based on the metal-ferroelectric-insulator-semiconductor (MFIS) structure with HfxZr1−xO2 (HZO, 0.5≤x≤0.9) thin film. The results indicate that the NCFETs exhibit excellent subthreshold swing (SS) values, consistently below 60 mV·decade−1, which is the theoretical physical limit of conventional Si-based field-effect transistors (FETs). The ferroelectric HZO composition significantly influences the longitudinal electric field, electron concentration, and hole concentration within the channel, thereby directly affecting the SS and saturation current. Notably, the MFIS NCFET incorporating an Hf0.5Zr0.5O2 ferroelectric layer exhibited the lowest SS. Moreover, by modifying the dielectric material and channel length, variations in the trends of SS and saturation current were observed. The device with ZrO2 dielectric layer, characterized by the highest dielectric constant, demonstrated the lowest SS of 47.49 mV·decade−1. Furthermore, the SS decreased as the channel length increased from 50 nm to 1000 nm. This research provides theoretical support for the performance optimization of low-power NCFETs and negative capacitance capacitors.
With the rapid advancement of artificial intelligence technology, the scale of data to be processed by computers is growing exponentially, imposing increasingly stringent demands on the performance of computer hardware storage. The read and write speeds of conventional flash memory can no longer match the computing speed of central processing units (CPUs), creating the "memory wall" bottleneck that severely limits further improvements in computing performance. Meanwhile, the trend toward mobile and portable high-end consumer electronics has raised increasingly stringent hardware requirements, particularly for ultra-low-power operation, high integration density, and cost-effective data storage solutions. Since the discovery of ferroelectricity in doped hafnium oxide (HfO2) thin films, HfO2-based ferroelectric materials have attracted considerable attention in the device engineering community. Owing to the excellent compatibility and scalability of HfO2 thin films with modern semiconductor manufacturing processes, ferroelectric field-effect transistors (FeFETs) have re-emerged as a key focus in advanced microelectronics, becoming a key candidate device for breaking through the performance bottlenecks of traditional memory and overcoming the "Memory Wall" dilemma. This paper focuses on the application of FeFETs in non-volatile memory, systematically elaborates on their basic operating principles, and deeply investigates the influence laws of doping effects, annealing processes, cooling rates and other factors on the ferroelectric properties of hafnium oxide thin films. Aiming at the reliability issues of FeFETs, particular emphasis is placed on analyzing the mechanisms and strategies for enhancing critical device performance metrics, such as memory window, endurance, and data retention time. Furthermore, this paper briefly reviews the latest research progress of FeFETs in terms of material optimization (such as hybrid ferroelectric layers and novel high-k interlayers) and structural innovation (such as indium-gallium-zinc oxide based FeFETs). Finally, the future development of FeFETs is prospected, indicating that hafnium oxide-based FeFETs hold important commercial application prospects in the fields of embedded non-volatile memory, neuromorphic computing, high-density storage and so on, and are expected to become the core component of the next-generation microelectronic memory devices.
To achieve effective and controllable modulation of the electrical performance of WSe2 field-effect transistors (FETs), ultraviolet-ozone (UVO) treatment was employed to modify the surface of mechanically exfoliated WSe2 flakes and their corresponding devices. Compared with untreated samples and those subjected to oxygen plasma treatment, no obvious changes in surface morphology or material thickness were observed after UVO treatment, indicating that this method introduces negligible physical damage to WSe2. Results from Kelvin probe force microscopy (KPFM) and electrical characterization indicate that UVO treatment effectively reduces the surface potential and increases the work function of WSe2, resulting in a pronounced shift of the transistor threshold voltage toward zero gate bias. Benefiting from these modifications, the carrier mobility of the devices is significantly enhanced from 1.37 cm2·V−1·s−1 to 2.61 cm2·V−1·s−1. These results demonstrate that mild UVO surface modification provides an effective and facile post-treatment strategy to improve the electrical performance of WSe2 FETs while preserving the structural integrity of the material, offering a novel approach for post-treatment processing of high-performance two-dimensional electronic devices.
