In the present study, a newly designed polyester substrate-based textile microstrip patch antenna operating in the 3.5 GHz band is proposed for smart clothing in broadband wireless applications. The motivation behind this work stems from the lack of comprehensive studies that address all critical aspects—including off-body performance, fabrication, testing, on-body evaluation, bending analysis, and SAR assessment—while specifically focusing on polyester textile antenna designs for the 3.5 GHz band in next-generation wearable systems. The antenna of small dimension 30×20×0.8 mm³ is designed and simulated in CST, followed by prototype fabrication and subsequent measurements to validate the simulation results. Slotting and partial grounding techniques are employed in the design for improving the radiation performance of the antenna. The effectiveness of the antenna has been assessed under the off-body and on-body conditions. Bending analysis under various bending conditions is performed to assess the antenna’s flexibility and suitability for wearable applications. Experimental results obtained from the fabricated antenna in free space and on-body scenarios show agreement with simulation data. Moreover, the specific absorption rate (SAR) analysis confirming that the antenna complies with IEEE safety standards. The proposed antenna achieves a wide bandwidth of 1.17 GHz (operating range of 3.11-4.27 GHz), a higher radiation efficiency of 94.52%, and a moderate peak gain of 2.59 dB. It covers 5G NR (n77, n78), C-Band (Radar/WiMAX), CBRS, and Extended C-Bands used for wearable broadband applications. Hence, the proposed antenna is robust and well-suited for smart clothing applications in wireless broadband applications as it combines good radiation characteristics and stable performance under bending, while maintaining safe SAR levels and a compact textile-compatible design.
On the last day of February 2026, Prof. Milić Stojić, a long-standing member of the Editorial Board of the Electronics journal, passed away. During the first few years following the establishment of the journal in 1997, he encouraged many authors of the best papers presented at the regional conferences to publish their work in the journal. He served as Guest Editor for Vol. 2, No. 1. He also recommended distinguished international scientists to contribute invited papers, which significantly helped the journal gain recognition relatively quickly, at first throughout the region of the former Yugoslavia and subsequently around the world. On the occasion of Prof. Milić Stojić's 70th birthday, we dedicated Vol. 15, No. 1 of the journal to him. In that issue, we published his biography, which we provide here in a slightly modified form.
In order to improve operational efficiency for lowpower VLSI (Very Large Scale Integration) designs, the current research presents a simulation-based comparison of the results of basic gates, computation-intensive circuits, and basic memory blocks designed using FinFET technology. This creative designs in multipliers effectively consolidates input data by stacking blocks, which significantly reduces time in next-stage operations. To assess the suggested compressor design in terms of average power, delay, and Power Delay Product (PDP), extensive simulations and analyses are carried out. When conducted within the same technological and environmental conditions as existing designs, proposed designes demonstrate clear advantages. The proposed compressor shows an amazing 64.91% decrease in delay, a significant 87.85% improvement in average power consumption, and a notable 95.74% improvement in energy efficiency for proposed 4-3 compressor and similar outcomes for 5-3 compressor. In memory design, it also demonstrates a notable enhancement, achieving an 87.95% reduction in average power, a 49.57% decrease in delay, and an 87.57% improvement in Energy Delay Product (EDP) compared to both conventional NAND-based and FinFET-based Content Addressable Memory (CAM) designs.
The biosensor capable of detecting COVID-19 (SARS-CoV-2) viruses in the terahertz (THz) regime has the potential to revolutionize virus detection and diagnosis. One effective approach is the utilization of a new type of sensor called a multi-band metamaterial. These metamaterials are artificially engineered materials that exhibit properties not typically found in natural substances. They consist of sub-wavelength structures designed with precise electromagnetic properties. Multi-band metamaterial sensors can simultaneously detect multiple frequencies of THz radiation, increasing the likelihood of virus detection. These sensors offer several advantages, including high sensitivity, non-destructiveness, and the ability to accurately detect even small amounts of virus particles. Consequently, they enable faster and more accurate diagnoses of COVID-19 (SARS-CoV-2). In the THz regime, the biosensor employs a novel multi-band metamaterial resonator that incorporates a thin gold layer (35nm). The resonance frequency and parameter S11 (dB) of the sensor exhibit sensitivity to changes in the refractive index of the sample. This sensitivity allows for precise and reliable detection. The study demonstrated that our sensors exhibit minimal frequency offsets, compact electrical dimensions, high sensitivity, and a linear relationship between the sensor’s resonant frequency and refractive index, enhancing their effectiveness. The proposed structures have demonstrated the ability to detect COVID-19 viruses with an average sensitivity of 347.7GHz/RIU (2.154dB/RIU). This biosensor can differentiate between different types of COVID-19 viruses, further highlighting its potential in virus identification and classification.
Antennas offering wide bandwidth, high gain and efficiency are essential to terahertz (THz) wireless communication systems and has gathered significant attention in antenna research. This paper introduces a compact, high-gain, ultra-wideband (UWB) microstrip patch antenna tailored for THz applications, along with its performance analysis. The proposed antenna has an elliptical patch with a pi shaped slot and is excited by a tapered feedline. An elliptical patch antenna incorporating a pi-shaped slot is introduced for the first time in the terahertz THz spectral region, demonstrating the ability to simultaneously achieve substantial size miniaturization, wideband performance, improved impedance matching, and enhanced gain. The antenna structure was designed and optimized for improved performance using CST Microwave Studio (MWS) version 2018. A Rogers RT/duroid 5880 substrate was used for antenna design, featuring 6 μm thickness, 2.2 relative permittivity, 0.0009 loss tangent, and 120 × 80 μm² planar dimensions. The proposed antenna demonstrates strong performance characteristics with a wide impedance bandwidth of 3.41 THz (5.01–8.42 THz), high gain of 7.906 dB, radiation efficiency of 77.83%, and low return loss of −43.57 dB, with consistent VSWR across the entire frequency range. The surface current distribution as well as the input impedance of the pi-shaped slotted antenna are also favorable. All the simulation results suggest that the proposed small size pi-shaped slotted elliptical patch antenna can be a suitable candidate for high-speed 6G wireless communication applications in the THz band.
This study introduces a new perspective into deep learning in the light of a multimodal approach: cardiovascular events can be predicted, using real-time data of physiological signals in collaboration with metadata related to the patient. Electronic Health Records (EHR) are digital versions of patients’ medical histories, while Multilayer Perceptron (MLP) and Convolutional Neural Network (CNN) are deep learning architectures designed for processing structured data and spatial/temporal patterns, respectively. A hybrid neural network model is designed that allows taking, as input from the CNN, the 12-lead ECG signals, while an MLP processes patient demographic and clinical features. It is designed to simultaneously process temporal ECG patterns and static patient characteristics for all-rounded cardiovascular risk assessment. In this work, our dataset consisted of 17,441 ECG recordings per patient, each being a 12-channel signal sampled on 500-time points and patient metadata like age, sex, and weight. Our architecture has two specialised components: the proposed SignalCNN to process the waveforms including two convolutional layers with batch normalization and dropout as regularization and MetaMLP processing patient metadata. These combined features are then fed into a classifier to enable multi-label prediction of five common cardiovascular conditions. The model yielded very promising results and performed very robustly with an overall validation accuracy of 85.19% after 15 epochs of training. The training was improving smoothly for both training and validation metrics, while the validation loss decreased from 0.4298 to 0.3484, which is indicative of good generalization. The model was very stable in its training without showing any hint of overfitting thanks to strategic dropout and batch normalization. This work will contribute to cardiovascular healthcare with a real-time, automated system that can be used for the early detection of cardiac events. The approach is multimodal, offering more nuanced predictions by including instantaneous physiological signals, together with patient-specific factors. This may enable earlier and more accurate clinical assessment of cardiovascular risk.
As technology scales down CNTFET (Carbon Nano Tube Field Effect Transistor) circuits has gained importance in VLSI design due to exacerbation of process parameter variations in CMOS. Particularly design of SRAM cell needs more attention as it occupies the larger space in CPU of the battery powered wearable devices. Hence it is a challenging task to the chip designer because the power, energy, speed and stability of the memory cell has a greater impact on system CPU efficiency. A variation tolerant nine transistor CNTFET SRAM cell is proposed in this work. Metrics considered for investigating the proposed SRAM performance is power, delay, power delay product (PDP) and static noise margin (SNM). Stanford University 32 nm CNTFET model and HSPICE tool is utilised for the simulation. In proposed SRAM the read and write power reduction is improved by 4.7x and 9.9x respectively, while the read delay and PDP reduction is improved by 10x than conventional SRAM. The hold, read and write stability of proposed memory cell is enhanced by 1.4x, 1.2x and 4.1x respectively compared to conventional structure.
The challenges of traditional quantitative irrigation methods cannot adapt to the dynamic actual soil moisture content and meteorological changes, and the existing methods based on soil moisture thresholds cannot fully solve the problems of hysteresis and adaptability, lack comprehensive consideration of meteorological factors and growth dynamics, and fail to consider the subtle sensitivity to soil moisture changes and processing efficiency limitations. To address the above challenges, we propose UFOGCN- SPANet, a novel and computationally efficient architecture specifically designed for resource-constrained precision agriculture. Its core innovation lies in the cascaded integration of: (1) a linear-complexity Unit Force Operated Vision Transformer (UFOViT) that replaces quadratic self-attention with matrix associativity and cross-normalization for efficient global spatio-temporal feature extraction; (2) Graph Convolutional Networks (GCNs) for modeling spatial dependencies; and (3) a Salient Positions-based Attention Network (SPANet) employing a novel Significant Position Selection (SPS) algorithm to dynamically focus computation on the most informative contextual features, drastically reducing complexity while enhancing discriminative power. This unique combination directly addresses the critical challenges of computational efficiency and effective context modeling in real-world irrigation systems. Experimental results show that the proposed method outperforms traditional GNN models such as SAGEConv with 12 standard time series forecasting methods in key metrics, including accuracy, precision, recall, and F1-Score.
As computers develops, virtual simulation technology becomes an important means of integrated circuit design. Therefore, based on the demand for virtual simulation of integrated circuits, a simulation method combining affinity propagation and differential evolution algorithm was proposed. By applying the affinity propagation to circuit fault diagnosis and combining it with differential evolution algorithm, circuit parameters optimization was carried out. These experiments confirm that the fusion of affinity propagation and differential evolution algorithm has a precision of 94.26%, recall of 93.41%, mean F1 of 88.59%, convergence speed of 56.77 seconds, and stability of 93.17%. The affinity propagation performs well in clustering. Especially without pre-defining the classes, it can identify the position and number of class centers automatically. The simulation of integrating affinity propagation and differential evolution algorithm has broad application prospects in virtual simulation of integrated circuits. It can improve simulation effectiveness and performance, providing effective support for circuit design and testing.
Hardware-intensive signal processing has seen tremendous growth over the last few decades, owing to the advances in VLSI technology. This has resulted in a significant paradigm shift, wherein different computational functionalities are increasingly implemented using different hardware platforms. The squaring function is one such operation that finds its application in many signal-processing tasks. Since squaring is a specific case of multiplication, traditional multiplication algorithms can be adapted to create high-performance squaring architectures. In this paper, we present a squaring architecture that is based on the CORDIC algorithm. The hardware efficiency of the CORDIC algorithm enables it to compute different mathematical functions using only shift and add operations. By operating the algorithm in linear mode, the CORDIC computations can be modeled to emulate the squaring function. Our 8-bit CORDIC-based squaring architecture shows a 25% and 38% reduction in PDAP over the existing best design for ASIC and FPGA platforms, respectively.
The present work explores the insights of a design which is defined as an octagonal geometry based four port wideband MIMO antennas for wireless systems. The isolation essentialities have been considered through the parasitic elements (PE) with T-shaped isolation structure for isolation boost. The antenna under consideration is optimized to achieve the best MIMO performance parameters. It has functional band of 2.16-4.30 GHz and the antenna fabricated on substrate size of 60.0 X 76.0 mm2. The gain 3.44 dBi, envelop correlation coefficient (ECC) < 0.03, and mean effective gain (MEG) ≤ -2.90 dB are achieved. The total active reflection coefficient (TARC) bandwidth is found 1.35 GHz. The specific absorption rate and channel capacity loss are evaluated, and both found to be within acceptable limit recommended by international telecommunication union (ITU). The results obtained through the proposed design are found to be within the acceptable limits of stability for effective communication system.
Singular Spectral Analysis (SSA) is a computationally intensive approach to denoise and detect a time-series signal. It requires the evaluation of eigenvalues and eigenvectors of a covariance matrix, which is the computationally intensive step in the SSA algorithm. The current work presents a feasible approach to implement the algorithm in embedded hardware using a PYNQ-Z2 Field Programmable Gate Array (FPGA) board. We implemented the algorithm using both the Processing System (PS) and the Programmable Logic (PL) of the PYNQ-Z2 System on Chip (SoC) with the help of a High-Level Synthesis (HLS) tool. A case study is carried out on a Nuclear Quadruple Resonance (NQR) signal. The implementation result demonstrates a hardware acceleration of 15.48x with respect to the equivalent software implementation of the algorithm on the ARM Cortex-A9 processor.
This paper reports the influence of magnetic tunnel junctions on the electrical response of an operational amplifier (op-amp) circuit. As a baseline, the pure-CMOS operational amplifier has been designed using the 180 nm semiconductor process technology from the Taiwan Semiconductor Manufacturing Company Ltd. and the test bench has been simulated to obtain circuit performance metrics like open loop gain, phase, bandwidth and phase margin. The introduction of a magnetic element can upset the electrical behavior and the same has been observed with the introduction of Fe-MgO tunnel junction on the baseline electrical behavior of the operational amplifier test bench. Possibilities of connecting the tunnel junction to the different nodes of the opamp test bench have been explored and the consequent drifts in the electrical response have been studied in this paper. Furthermore, an attempt has been made to mirror the transistors in the op-amp circuit with tunnel junctions and the consequent electrical responses have been studied in this paper. Such a magneto-CMOS hybrid circuit configuration can be used for a wide range of novel applications that demand a higher packing density in limited die area.
Unmanned Vehicles (UVs) and the Industry Internet of Things (IoT) are two examples of new technology being incorporated into manufacturing processes during the fourth industrial revolution. IT networks must be machine-compatible to integrate these technologies; this includes addressing problems with connectivity, fog, and cloud-based computing security, lowering latency, and improving data reliability and standard of service. Regarding IoT, AI techniques must handle resource management, network deployment, and these problems. The significant issues are unstable and high-latency communications between Industrial IoT endpoints and the Cloud. By extending storage and computation to the network’s edge, fog computing offers a valuable tool for merging intricately linked processing systems. Interoperability may be addressed using fog in an IoT gateway and advanced software distributed on the edge. However, as an IoT gateway is essential to processing and delivering data to many systems and platforms, selecting one is critical regarding accuracy and latency. Intelligent IoT monitoring and real-time control based on Integrating Autonomous Robots for Instantaneous Industrial Operations, visual recognition, and cloud/edge computing services are proposed to address these challenges. By deploying Deep Learning (DL) facilities close to customers who want them, latency and processing costs associated with transmitting data through the Cloud may be minimized. The suggested methods enhance platform decision-making and industrial automation system performance by integrating cloud-based services into an operational loop. A smart approach that offers a trade-off between accuracy and latency is suggested to choose the right AI for the situation under observation.
The paper provides an extensive experimental analysis of an optimal PI controller for the two-tank system. The two-tank system is a benchmark hydrodynamic system. The PI controller has proportional action placed in a feedback path of the system, thus supporting aperiodic response of the system. The optimal PI controller tuning is based on transfer function of the system, and it minimizes surface between the error signal and the time axis. The choice of the minimization criterion is adequate as the system has aperiodic step response. The extensive experimental analysis is performed on the laboratory testbed to assess the performance of the optimally tuned PI controller when applied to the two-tank systems in step response tasks, reference tracking tasks, and disturbance rejection tasks. The results of the experiments verify the design procedure of the PI controller. The designed PI controller provides noticeable slow start of the system, thus forcing an actuator to operate on a border line of the dead zone for a significant period. To remedy the situation, a feedforward modification of the controller is proposed. Gain of the feedforward part is time varying. At the beginning of the system operation, it provides significant value of the control signal and safe start of the system. On the other hand, as time advances, the gain of the feedforward part vanishes to zero. Although the feedforward modification detunes optimal behavior of the system, it adds value to the operation of the system. Experimental analysis performed on the laboratory testbed verifies utilities introduced by the feedforward controller modification.
The Internet of Medical Things (IoMT) offers diverse application support through monitoring, analysis, and recommendations. This application paradigm relies on sensitive internal and external data to meet user needs. This article introduces a secure data processing scheme for leveraging the IoMT application performance. This scheme is named Persuaded Data Processing with Digital Security (PDP-DS), ensuring user and data privacy. This scheme focuses on IoMT-aided remote monitoring application security where data openness is high and false data chances are high. During the application support, the blockchain concept is applied for data authentication. In this scheme, user-verified digital signatures are used for authentication. This scheme provides data processing recommendations based on the deep learning paradigm. This output is authenticated alone using a password/ PIN-based digital signature. The learning process identifies the processing required and security-filtered instances using the recursive states identified. The proposed scheme ensures fewer false data processing based on its attributes and recommendation factor. PDP-PS reduces the considered metrics to 9.95% (for process delay), 10.19% (for service delay), 10.6% (for replication factor), 10.44% (for false rate), and 7.39% (for backlogs).
This present work aims to contribute to the solution of the problems encountered in electronic circuits fault diagnosis. One of these troubleshoots faced is the lack of effective features that help to optimize fault classifier and hence improve circuit fault detection and identification. Thus, our feature extraction approach is based on the CUT’s transfer function. This is deduced from the Matlab identification system IS model (ISM), namely the OE model belonging to the ARMA model’s family. These features are the transfer function polynomial coefficients playing a crucial role in the fault free and faulty circuits construction models and feeding the classifier for the fault diagnosis purpose. The faults we are dealing with are of single parametric type. This is done from PSPICE time domain analysis on the CUT output response under theses circuit conditions and followed by extracting the IS model (ISM) orders (p,q) polynomials. The coefficient values of the latter were considered as efficient comparison elements between faulty and healthy circuit responses. As a result, the OE model has achieved 100% fault coverage and its construction reached high accuracy level exceeding 98% for faulty circuits. This accuracy level ambition us to use its coefficients as input features for our Hybrid proposal fault classifier. This is built with GA and SVM algorithms combination targeting both data reduction and fault classification accuracy respectively. The results achieved are conclusive since the classifier accuracy level reached 100% and a 70% of feature data volume reduction was scored.
As deep learning models become more prevalent in smart grid systems, ensuring their accuracy in tasks like identifying abnormal customer behavior is increasingly important. As its use is increased in smart grids to detect energy theft, crafting adversarial data by attackers to deceive the model to get the desired output is also increased. Evasion attacks (EA) attempt to evade detection by misclassifying input data during testing. The manipulation of data inputs is done so that it is not noticeable to humans but can cause the machine learning (ML) model to produce incorrect results. Electricity theft has become a major problem for utility companies that need to be dealt with effectively. Convolutional Neural Network (CNN) and AdaBoost hybrid model have been developed that promise to detect electricity theft with high accuracy. However, this model is also vulnerable to evasion attacks that can render it ineffective. In this paper, to make the detection system more robust, we present a generative method to create evasion attacks against a hybrid model combining Convolutional Neural Network and Adaboost (CNN-Adaboost). Generated adversarial data from the proposed algorithm is crafted on the model to test its performance. Our proposed attack is validated with State Grid Corporation of China (SGCC) dataset. We test the CNN-Adaboost energy theft detection model and other models’ performance under 5% and 10% evasion attacks. Our findings reveal model performance degradation under our proposed generative evasion attack ranging from 96.35% to 89.23%. With the defence mechanism, we successfully increased adversarial accuracy by up to 97% and decreased the attack success rate (ASR) by up to 3%. These adversaries are useful for designing robust and secure machine learning models, offering an improved solution compared to previous work in this area. We tested the model with varying percentages of adversarial data to analyze its behavior effectively. These adversaries are useful for designing robust and secure ML models. The proposed attack and defence can be utilized to test energy theft detection (ETD) models in industrial and commercial settings.
Two-dimensional (2D) Convolution is frequently used in many image processing applications like image smoothening, image sharpening, feature extraction, image enhancement, object recognition, etc. Although the operation of 2D Convolution is simple, its hardware implementation is quite challenging due to enormous computational and memory costs. Various 2D convolution implementations have been proposed in the literature. Among them Separable architectures stand out in terms of the reduction in the computational complexity. However, these have not been extensively explored in the literature, and more research needs to be done, especially for applications that are constrained in resources. This paper presents a novel separable Convolution architecture based on the folding transformation. The application of the folding transformation technique yields a resource-efficient architecture by time multiplexing the different functional units within the separable Convolution operation. The hardware implementation is done using Xilinx Artix-7 xc7a35tcpg236-1 FPGA device. The proposed architecture offers benefits over the existing architectures regarding on-chip resource utilization, power consumption, critical path delay, and external memory bandwidth (EMB).
The logical effort method is a technique for accurately estimating the delay of a CMOS circuit. This method is computed as a ratio of capacitances. In this work we propose a low-power full adder circuit and compare it with three established low power full adder circuits. The circuits were designed utilizing Cadence Virtuoso software and GPDK 45nm technology. A comparison was conducted based on delay, average power, power delay product, and transistor count. In this work, all circuits are resized to achieve minimum delay according to the logical effort. It has been shown that the proposed design (design 4) is showing better performance in terms of average power, delay of sum and delay of carry than other designs by 34.23%, 26.81%, and 4.33%, respectively.
