The transconductance and the transresistance modes might act as the bridge transferring from voltage mode to current mode and vice versa, respectively. This paper presents a new mixed-mode (including voltage, current, transconductance, and transresistance modes) high-order universal filter structure using n+1 differential difference current conveyors (DDCCs), n grounded capacitors and n+2 grounded resistors, which are the minimum components necessary for realising an nth-order mixed-mode universal filtering response (low-pass, high-pass, band-pass, band-reject, and all-pass) from the same topology. Moreover, the proposed circuit simultaneously achieves nearly all of the main advantages. H-Spice simulation results confirm the theory.
To meet the demand of the state-of-the-art high-speed double data rate systems, the precise system timing plays an important role since both rising and falling edges of the system clock signal are employed to sample the input data. Owing to this requirement, it is necessary to accurately maintain the duty cycle of the clock signal at 50%. A pulsewidth control loop (PWCL) circuit was therefore proposed to adjust the duty cycle of the output signal of a multistage clock buffer. The main theme of the paper is aimed at introducing a newly proposed differential PWCL (DPWCL) together with investigating its mechanism through a comprehensive theoretical analysis that also demonstrates the settling speed of the proposed DPWCL is much faster than the conventional PWCL. Alternatively, the proposed DPWCL employs a low-pass filter to generate the reference voltage for the balanced charge pump so that the DPWCL does not necessitate a 50% duty cycle reference clock. A duty cycle tuning mechanism based on the proposed DPWCL is also presented.
A high efficiency and low distortion switching power amplifier is proposed. This circuit is designed for micropower low-voltage hearing aids. The experimental results show that the proposed circuit has 0.27% total harmonic distortion and 90% power efficiency while the d.c. output bias current ( for R-L = 600 Omega) is 19 mu A at 1.5 V supply voltage.
Approximation and design methods of a general class of IIR complex functions without any required symmetrical property are examined. A set of routines has been developed to allow arbitrary amplitude approximation of such asymmetrical functions. Approximation routines will include such features as high-order touch points in both passband and stopband regions, fixed poles and zeros and arbitrary frequency template shaping. These features, in conjunction with a Remez approximation algorithm, will permit the development of functions that realise any reasonable arbitrary shape and form of the transfer function. Approximation routines have been implemented in the XFILTER design software and a number of examples, demonstrating efficiency and flexibility of the proposed approximation method are presented. One fully integrated circuit design of a general complex function is shown. It is realised in the log domain since this technology shows good potential for design of low-power, high frequency and high-dynamic range networks
A new microwave voltage-variable attenuator integrated circuit operating from 1.0 GHz to 3.5 GHz with a large attenuation range is demonstrated in this work. The input signal enters an active balun circuit, which generates an in-phase (0 degrees) signal and an out-of-phase (180 degrees) signal of equal amplitudes. The signals then pass through a pair of source-follower buffer circuits and then through two common-gate (CG) NMOS devices. The drains of the two CG circuits are connected together at the load. While one CG transistor is kept fully on, the gate bias of the second CG device is varied and the amplitude of the signal passing through it changes. Therefore, when the two signals emerging from the CG transistors are added at the output, variable attenuation occurs. The circuit exhibits a measured attenuation range of approximately 30 dB. The I dB compression point occurs at an input power of - 13 dBrn when the attenuation is set to 12 dB. The second harmonic is suppressed by at least 20 dB up to the 1 dB compression point and the measured IIP3 is 3 dBm. The IC was implemented using 0.18 mu m CMOS technology. The circuit measures 575 mu m by 275 mu m including bonding pads and it consumes 18 mW of DC power.
A charge pump that changes its number of stages while maintaining the same total charge pump capacitances is presented. The charge pump dynamically modifies the number of stages through a feedback that rearranges the topology of the set capacitor minimising power consumption. The circuit is then discussed analytically and validated through transistor-level simulations by using 0.18 mu m EEPROM technology.
This paper presents a heuristic approach to accelerate the reconfiguration of two-dimensional degradable VLSI arrays linked by 4-port switches in presence of faulty processing elements (PEs). In particular, we proposed a technique to preprocess the host array by 1) identifying fault-free PEs that cannot form the target array due to their proximity to faulty PEs, and 2) labeling these fault-free PEs as faults. The proposed preprocessing method minimizes the number of PEs that will be considered for reconfiguration, thus accelerating the reconfiguration process. Simulation results show that the runtime of two well-known algorithms are significantly reduced by employing the preprocessing technique. In addition, we demonstrate the scalability of the proposed technique by showing that the runtime reduction rate increases with increasing fault density.
Two strategies to enhance transistor performance in SOI technology without increasing the operating voltage are compared. The first option is the use of the self-cascode transistor, a series connection of two conventional FD SOI MOSFETs which, with an appropriate choice of sizes, work as a single transistor with reduced output conductance. The second option is the use of the graded-channel (GC) SOI MOSFET, consisting of a modification of the fully-depleted (FD) SOI MOSFET which leads to better performance of the device in saturation. The paper shows the existing analogy between the operation of self-cascode and GC SOI transistors. The comparison between both strategies is carried out on the basis of simulations with the University of Florida SOI (UFSOI) model and experimental measurements. The area consumed by a self-cascode SOI transistor is estimated to be 10 times larger than that of a GC SOI transistor for the same improvement in output conductance. Experimental results validate the model used for the GC SOI device and also provide numerical quantification of output resistance increase in both configurations.
An analytical model for evaluating the bias-dependent and dynamic drain coupling ratio of the drain-coupling source-si-de injection split gate flash is developed with comparisons of classical extraction methods. A new method to measure the technology-dependent select gate coupling ratio is also presented. Starting with the quasi-two-dimensional analyses on separate channel regions, the channel potential distributions are utilised to derive the analytical expressions of the drain coupling ratio as functions of the applied bias and storage charge. In good agreement with the experimental programming transient, full dynamics of the analytical drain coupling ratio not only explain the discrepant experimental results from classical extraction methods but also provide a solid base on designing split gate devices. Additionally, the characteristic lengths and saturation voltages of high field regions are extracted by the substrate current and the programming transient. A mean free path of about 92 A and a impact ionisation field of 1.74 MV/cm are also verified from the source-side injection device.
The influence of Joule heating on current filaments evolving during the reverse recovery phase in high-power diodes is analysed by electro-thermal Simulations. Depending on the turn-off conditions, transitions of the uniform current-density distribution into a quasi-static filament, a travelling filament, or a periodic current-density distribution may occur. Simulations show under which conditions a pure electronic mechanism or Joule heating may cause the evolution of travelling current filaments. In general, strong local heating favours the transition of static into travelling structures. Under certain conditions, the simultaneous activation of the electronic and the thermal mechanism may lead to the coexistence of filaments travelling with different velocities.
Quantum-dot cellular automata (QCA) is a novel computing mechanism that can represent binary information based on the spatial distribution of electron charge configuration in chemical molecules. QCA circuit layout is currently restricted to a single layer with very limited number of wire crossings permitted. Thus, wire crossing minimisation is crucial in improving the manufacturability of QCA circuits. We present the first QCA node duplication and routing algorithms for wire crossing minimisation. Our duplication algorithm named fan-out tolerance duplication (FTD) explores node duplication in conjunction with node placement using K-layered bipartite graphs (KLBG). FTD successfully removes additional crossings at the cost of increased area and allows flexible tradeoff between area and wire crossing. Our routing algorithm, namely cycle breaker (CB), constructs a modified vertical constraint graph (VCG) to enforce additional vertical relation for wire crossing reduction. We formulate and provide a heuristic solution for the weighted minimum feedback edge set problem to effectively remove cycles from the VCG. As a result, FTD and CB achieve wire crossing results that are very close to theoretical lower bound and outperform the conventional algorithms significantly
The sequence-pair, a data structure with applications in packing-based VLSI module placement, has received significant amounts of research effort as the core of simulated annealing optimisers. Nevertheless, its application within genetic algorithm frameworks has not been adequately investigated. This paper presents a genetic algorithm approach to rectangle packing using the sequence-pair. The method is extended to handle symmetry constraints, a requirement often arising in the placement of analogue circuits. Genetic operators are developed taking into account the specific properties of the sequence-pair, and the algorithm is tested on several MCNC benchmarks
The use of external forcing to influence the dynamics of RCL-shunted Josephson junction is reported either to control chaos or to synchronise two identical coupled junctions. The frequency of an external periodic signal is used as the control parameter for taming or suppressing chaos in a junction. Numerical investigations show that the junction oscillation is amplitude modulated at forcing frequencies much lower than the natural frequency of the junction. When the forcing frequency is increased to a higher range close to the natural frequency of the junction, phase locking (n: m) of the sinusoidal forcing is observed. Two important routes to chaos, period doubling and torus breakdown are observed as the forcing frequency range is changed. Synchronisation of two identical junctions is implemented using an external negative pulsing.
The proposed scheme, called the IOC-LP (input reduction and one block compression for low power test), compresses the test data of scan based SoCs to improve the compression ratio in the ATPG process. It does so by using the modified input reduction and novel techniques, a new scan flip-flop reordering for low power test, the newly proposed one block compression, and a novel reordering algorithm. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is able to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed method leads to a better compression ratio with lower hardware overhead and lower power consumption than previous works. Experimental results on ISCAS '89 and ITC '99 benchmark circuits validated the proposed method.
Latches and flip-flops play important roles in the building of digital CMOS circuits. In the paper, a new low-power positive level-sensitive latch and a simple and innovative dynamic pulse generator are proposed. The pulse generator is then used with the proposed latch to create a low-power and high-performance single edge-triggered flip-flop (SETFF). The proposed positive level-sensitive latch deploys two non-precharge (static) n-stages (SN) in a true-single-phase-clocking (TSPC) scheme. We therefore named our latch SN2. This is because the TSPC latches have the advantage of single clock distribution, less clock routing area, high-speed and no clock skew. Based on the 0.18-μm single-poly six-metal CMOS technology, the SPECTRE simulation results derived for typical input activities showed that the latch can attain a maximum power saving of 29.1% when compared to other reported designs. As for our proposed flip-flop that is derived from the proposed SN2 latch with incorporation of a dynamic pulse generator circuit, it is able to outperform other reported works by about 16.2% to 67.4% for its power-delay product (PDPCQ) that is taken with respect to the clock-to-output delay. The two new designs are therefore suitable for used in low-power and high-performance CMOS VLSI/ULSI applications.
The effects of different buffer structures on the avalanche and post avalanche behaviour of high voltage silicon diodes under high reverse current conditions has been investigated. After the onset of avalanche, when the diodes are reverse biased, branches both with positive and negative differential resistance may occur in the device characteristics and depend sensitively on the doping profile of the buffer layer. By numerical device simulation the influence of relevant bulk doping and various buffer profiles on these static reverse characteristics are analysed to understand, clarify and illustrate the breakdown behaviour of high voltage pin-diodes. Based upon these considerations an effective restriction of the electric field maximum at the nn + -junction at the cathode side of the diode can be achieved by adapting the doping gradient of the buffer profile.
A novel technique named Signal Bypassing and Zero Insertion to design energy-aware asynchronous circuits in multi-rail encoding logic is developed. Several examples including pipeline components, multiplier, and counter are designed and simulated. The proposed technique has advantages in energy saving and delay reduction as well.
Charge injection in MOS switches in a deep submicron technology has been analysed. The analysis has been extended to the general case of including the conduction of the MOS transistor in the moderate and weak inversion regions, using a continuous and physical formulation based on the EKV model. SPICE simulations, based on the BSIM3v3 model, which ensures the charge conservation, have demonstrated the validity of our work.
The first analysis and synthesis equations for the newly introduced inverse Class-E amplifier when operated with a finite d.c. blocking capacitance and a finite d.c.-feed inductance are presented in the paper. Closed-form design equations are derived in order to establish the circuit component values required for optimum synthesis. Excellent agreement between numerical simulation results and theoretical prediction is obtained. It is shown that drain efficiency approaching 100% at a pre-specified output power level can be achieved as zero-current switching and zero-current derivative conditions are simultaneously satisfied. The proposed analysis offers the prospect for realistic MMIC implementation.
The authors develop a novel technique for blind source separation (BSS) of nonlinearly mixed signals. A new type of nonlinear mixture is derived where a linear mixing matrix is slotted between two layers of multiple mutually inverse nonlinearities. The paper discusses the separability of this new mixing model within the BSS context. This model further culminates to a framework where the separation solution integrates the theory of series reversion with the Weierstrass neural network and the hidden neurons are spanned by a set of mutually inversed activation functions. Simulations have been undertaken to support the theory of the developed scheme and the results indicate promising performance. The proposed method outperforms other tested algorithms in recovering both synthetic and the real-life recorded signals. The method of selecting the optimum order of the Weierstrass series has also been derived and implemented to balance the computational complexity and the accuracy of signal separation.
