This paper presents a lifetime-sensitive scheduling method. By shortening lifetimes of variables in scheduling phase, it can lighten register pressure in register allocation phase, lessen spill codes and result in more efficient object codes. The preliminary experimental results show that this method is an effective scheduling method.
An efficient assignment of tasks to the processors is imperative for achieving fast job turnaround time in a parallel or distributed environment. The assignment problem is well known to be NP-complete, except in a few special cases. Thus heuristics are used to obtain suboptimal solutions in reasonable amount of time. While a plethora of such heuristics have been documented in the literature, in this paper we aim to develop techniques for finding optimal solutions under the most relaxed assumptions. We propose a best-first search based parallel algorithm that generates optimal solution for assigning an arbitrary task graph to an arbitrary network of homogeneous or heterogeneous processors. The parallel algorithm running on the Intel Paragon gives optimal assignments for problems of medium to large sizes. We believe our algorithms to be novel in solving an indispensable problem in parallel and distributed computing
This paper surveys the program dependence analysis technique for parallel and/or distributed programs and its applications from the viewpoint of software engineering. We present primary program dependences which may exist in a parallel and/or distributed program, a general approach to define, analyze, and represent these program dependences formally, and applications of an explicit program dependence based representation for parallel and/or distributed programs in various software engineering activities. We also suggest some research problems an this direction
This paper introduces an algorithm that can generate huge node data flow by compiling existing programs. The purpose of this algorithm is to improve the speed of parallel processing and utilize the large amount of existing program resources. In addition, this idea of huge node data flow algorithm can also be used in distributed processing and multi-thread processing.
This paper presents a new rapid thread replacement mechanism which is important in multithread technology. Analysis to the memory system indicates that the memory utilization decreases with the increase of cache hit ratio. The parallelism between thread computation and thread replacement is found by analyzing their working processes. Based on these, we advance a rapid multithread replacement mechanism which overlaps the thread replacement with thread computation. More especially, with finite hardware contexts, this mechanism can play the same role of infinite contexts by tolerating the replacement overhead. By modifying the general thread switching model, we build the thread replacement model and evaluate this mechanism in theory and experiment methods. At last, we discuss the hardware implementation and put forward the problems to be resolved in the future.
Exact direction and distance vectors are essential for detecting hierarchical parallelism and examining legality of loop transformation for a multiple level loop nest. Much of this work has been concentrated on array references. Little has been done to address the problems of finding precise dependences between scalar references, except to use extended SSA form with factored use-def links. In this paper, we present a technique for calculating precise direction and distance vectors for scalar references within nested loops without using any forms of SSA. To do this, we use conventional use-def links in combination with joint dominator and joint postdominator relationships, which are extended from dominator and postdominator respectively in standard data flow analysis. The precision of dependence information gathered by our algorithm can not be achieved by traditional analysis of dominator or reaching definitions.
This paper proposes the design of a scalable memory-shared multiprocessing system SMMP which supports Client/Server mode. SMMP system is composed of two-level interconnection networks three-level memory subsystem and three-level I/O subsystem. There are many advantages in the design of our SMMP, such as scalabe, easy to implement and operate, general purpose, and large I/O throughput. It can be an excellent server for high-speed communication network.
The multithreaded processor-called Rhamma-uses a fast context switch to bridge latencies caused by memory accesses or by synchronization operations. Load/store, synchronization, and execution operations of different threads of control are executed simultaneously by appropriate functional units. A fast context switch is performed whenever a functional unit comes across an operation that is destined for another unit. The overall performance depends on the speed of the context switch. We present two techniques to reduce the context switch cost to at most one processor cycle: A context switch is explicitly coded in the opcode, and a context switch buffer is used. The load/store unit shows up as the principal bottleneck. We evaluate four implementation alternatives of the load/store unit to increase processor performance.
In this paper, an approach using least squares method for Callback implementation is presented. Experiments on Callback approved that Callback was not only effective in high-level metasystems but also in low level heterogeneous system
Although highly parallel distributed memory computers exist for several years, the operating systems used on them did not fit the requirements very well. Most of them are designed for sequential, shared memory parallel or distributed computers. Examples are Unix on the IBM SP/2 and Mach on the Intel Paragon. This results in poor scalability caused by inefficient communication primitives designed for wide area networks or by waste of resources due to huge kernels (e.g. 8 MB per node are reported for Mach an the Paragon, which is harmful especially in highly parallel systems with hundreds or thousands of nodes. With Cosy (Concurrent Operating System) we have shown that a well structured and carefully designed system can be small (70 Kb for the kernel 372 total memory usage per node), efficient (33 /spl mu/s for communication), and scalable (applications run efficient on up to 1024 processors).
In the course of the development of reactive systems often real time constraints have to be met. In such time critical applications heterogeneous multi-processor systems are used in order to fulfill these time constraints. This paper presents a hybrid partitioning method that uses a stochastic algorithm together with mixed integer linear programming. This method supports the development of time critical systems. We assume that the algorithm which has to be analyzed is given in the form of a so-called task-graph. The goal of the overall method is to fix for every task the processor that will execute it and the starting time of this execution. The main issue is a high-level synthesis-like method for constructing a problem-specific multi-processor board. The presented methods have been fully implemented and tested.
Fast and efficient communication is one of the major design goals not only for parallel systems but also for clusters of workstations. The proposed model of the high performance communication device ATOLL 1 features very low latency for the start of communication operations and reduces the software overhead for communication specific functions. To close the gap between off-the-shelf microprocessors and the communication system a highly sophisticated processor interface implements atomic start of communication, MMU support, and a flexible event scheduling scheme. The interconnectivity of ATOLL provided by four independent network ports combined with cut-through routing allows the configuration of a large variety of network topologies. A software transparent error correction mechanism significantly reduces the required protocol overhead. The presented simulation results promise high performance and low-latency communication.
In this paper, we present an original approach for the design and execution of distributed applications that require numerous tasks of variable grain. The approach is based on the concept of task cluster which is an entity that groups tasks with strong logical interaction and that guarantees efficient communications between them. We describe the implementation of the model, that mainly relies on the use of lightweight processes as support for the distributed tasks. We also illustrate the use of the proposed approach on real size applications where it has improved both the ease of design and the performance.
For a parallelizing compiler, mainly based on loop transformations, dependence information that is as complete and precise as possible is required. In this paper, we propose a generalized method for computing, in any multi-dimensional loop, information which proved to be useful in the case of irregular dependences. Firstly, we solve the basic problem of the existence of a dependence with an algorithm composed of a pre-processing phase of reduction and of an integer simplex resolution. If a solution exists, we compute by integer simplex the bounds of the distances associated with loop indices. Depending on the values of these bounds, we finally define problems consisting in evaluating the bounds of slopes of dependence vectors, which we solve by integer linear fractional programming. The amount of computation for each new problem is very low. This algorithm has been implemented as an extension of the Janus Test, which was presented in a previous work.
To design a parallel computer system, selecting an appropriate network is an important issue. This paper presents the simulation results on the performance of message passing interconnection networks used commonly in multiprocessor systems. Comparisons have been made on the performance of various inter-connection networks like crossbar, mesh, hypercube, tree and hypertree with wormhole routing. The performance factors compared include the throughput of these networks and message delay. To make a more general model for tree structured network, this paper present the definition of m-fold n-ary tree, which is the extension of the hypertree network.
This paper proposes an efficient parallel approach to texture classification for image retrieval. The idea behind this method is to pre-extract texture features in terms of texture energy measurement associated with a 'tuned' mask and store them in a multi-scale and multi-orientation texture class database via a two-dimensional linked list for query. Thus each texture class sample in the database can be traced by its texture energy in a two-dimensional row sorted matrix. The parallel searching strategies are introduced for fast identifying the entities closest to the input texture throughout the given texture energy matrix. In contrast to the traditional search methods, our approach incorporates different computation patterns for different cases of available processor numbers and concerns with robust and work-optimal parallel algorithms for row-search and minimum-find based an the accelerated cascading technique and the dynamic processor allocation scheme. Applications of the proposed parallel search and multisearch algorithms to both single image classification and multiple image classification are discussed. The time complexity analysis shows that our proposal will speed up the classification tasks in a simple but dynamic manner. Examples are presented of the texture classification task applied to image retrieval of Brodatz textures, comprising various orientations and scales.
A new VLIW architecture, called GPMB(Global Pipelining of Multi-Branch), is discussed in this paper. The GPMB architecture can handle branch-intensive programs efficiently. With the concept of next address Function, GPMB regards branching as correctly calculating the next address. The next address function is implemented by hardware and software in GPMB. A brief description of GPMB and a detailed example are included. A comparison with other architectures is also presented in this paper.
The accuracy of the data dependence analysis of a client program will decide in what an extent the compiler can unleash the power of the potential parallelism of the client program. Most of the current works on dependence analysis are based on the dependence equation and constraint inequalities of loop variable bounds (sometimes augmented with the direction vector). Unfortunately, they can not give an exact detection on the dependence which may greatly affect the parallel optimization of the client program when software pipelining technique is employed. In the paper, we give a more effective constraint inequality which could reflect the characteristics of software pipelining technique and will improve the power of dependence analysis of most of the current algorithms when applied to software pipelining.
In this paper, we argue that because of recent advance of network & CPU technologies, workstation clusters are poised to become the primary parallel computing infrastructure for science and engineering computing. After analyzing and comparing the communication performance of three popular networks: 10 Mbps Ethernet, 100 Mbps Ethernet and 640 Mbps Myrinet on an experimental workstation cluster, we point out that two main factors hinder the wider application of workstation cluster: low efficiency of communication system (both hardware and software) and lack of friendly parallel program development environment with accessory tools. For these two problem, we implemented two workstation cluster systems for different performance/price rate requirements: one is 8 PowerPCs with shared media network, another is 8 Sun Sparcstations with switch network. By using Reduced Communication Protocol (RCP), we dramatically improved the performance of communication system; by expanding the language support of PVM and adding several useful tools, we build a visual integrated parallel program development environment IPCE. On our platform, we also analyzed several massive applications, such as GRI benchmark, earthquake simulator, weather forecasting and some NAS benchmarks, and we get very good results for these coarse-grain to middle-grain applications. The speedup ranges from 5.83 to 7.98 and parallel efficiency reaches to 72.88%-99.7%.
