With the latest advances in digitalization and Industry 4.0, the manufacturing industry is collecting more and more production data. However, with the increasing interconnection of machines, not only the volume but also the variety of data is being expanded. The data life cycles of collection, processing, combining, analyzing and feeding new findings back into sources are becoming increasingly challenging for data scientists to complete. Reference architectures such as the RAMI 4.0 provide conceptual guidelines to address these problems. In this paper, we focus on the implementation of an agent-based architecture that is in line with RAMI 4.0. This architecture implements the guidelines provided by RAMI 4.0 by applying modern approaches from the areas of data lake based data acquisition, semantic description, look up and processing as well as information utilization.
Today Cellular Automata (CA) and Agent Based Model (ABM) based simulations are used to make predictions and discover properties of real world scenarios, e.g. predicting the spread of influenza contagions. In these situations it is important that we have maximum confidence in the simulations we employ. One factor that is known to affect the outcomes of a simulation is the choice of updating strategy used. Specific strategies can cause artifacts - i.e. outcomes of a simulation not due to any intrinsic properties of the model itself but caused directly by the updating strategy. To guard against artifacts multiple strategies should be used on a model and the outcomes compared. Currently, while both Synchronous and asynchronous updating are used in CA based simulations, AU is used almost exclusively in ABM. This is due to: (i) until recently, the lack of any well-known SU algorithm that can handle complex ABM interactions and (ii) belief that AU is a better model of how the real world works.
Amazon Elastic Compute Cloud (EC2) gives access to resources in the form of virtual servers, also known as instances. EC2 Spot Instances (SIs) offer spare compute capacity at steep discounts compared to reliable and fixed price on-demand instances. The drawback, however, is that waiting time until requested spots become fulfilled can be incredible high. In this paper, we propose a container migration-based solution to enhance the reliability of virtual cluster computing environments built on top of non-reserved EC2 pricing model instances. We compare the performance of our algorithm by executing different resource provisioning plans for running real-life workflow applications, constrained by user-defined deadline and budget Quality of Service (QoS) parameters. The results show that our solution is able to successfully conclude almost 98% of workflow applications and more than 99% of workflow tasks for on-demand- and spot block-based virtual compute environments. For SI-based virtual compute environments, our solution achieves similar results, completing more than 98% of workflow applications, and over 99% of workflow tasks, for a worse-case scenario.
Technical market indicators are used to measure the trends of financial markets. In practice they are conventionally expressed using a non-formal notation or a DSL specific to a certain development platform, which poorly correlates between individual trades and the high-level formulas operating on those trades and leaving very little room for optimization. In this paper we propose a formal, mathematically based notation for expressing technical market indicators, which represents trades as streams of data. We argue that this notation is more accurate and open to optimizations. We express three technical indicators from the ground up, demonstrate our optimization approach, and implement the indicators using Click router runtime. Finally, we benchmark various configurations and versions of the implemented indicators, running in kernel space as well as user space, and discuss the findings.
The world migration towards automatic and wire-less systems results an increased usage of Wireless Sensor Networks (WSNs). The noticeable popularity of WSNs has imposed enlarged computational in-node demands. Hence, the recourse to fully-integrated and sophisticated systems with low power is a challenging task. Since wireless sensor nodes have limited power resources, it is important to find a balance between energy consumption and computational performance. The traditional software optimizations are not usually suited or enough to find this tradeoff. Consequently, the use of codesign methodology and the careful implementation of hardware accelerator with low frequency processors could offer a good compromise between energy consumption and performance. In this paper, we present a SoC WSN node prototype based on Leon 3 processor for leak detection in water pipeline using Kalman Filter (KF). A hardware acceleration of the KF has been designed and implemented to reduce energy consumption. We have compared also the software implementation of the algorithm and its hardware acceleration in terms of the execution time, the energy consumption and the area requirements. The results show about 97% reduction in energy consumption and execution time without noticeable increased area.
This paper addresses the silo concern that undermines the participation of IoT-compliant things in composition scenarios. By analogy with composite Web services, each scenario is specified in terms of choreography and orchestration and at design-time and run-time. To define things’ execution behaviors during composition, a set of transactional properties known as pivot, retriable, and compensatable, are used allowing to decide when thing execution should be confirmed, rolledback, or stopped. Along with these properties, another set of availability properties known as limited, renewable, and nonshareable specify the resources that things consume at run-time. Not all resources are always available and hence, could impact the execution of thing composition scenarios. A case study related to Industry 4.0 is used to motivate thing composition.
In the field of neuromorphic computing several hardware accelerators for spiking neural networks have been introduced, but few studies actually compare different systems. These comparative studies reveal difficulties in porting an existing network to a specific system and in predicting its performance indicators. Finding a common network architecture that is suited for all target platforms and at the same time yields decent results is a major challenge. In this contribution, we show that a winner-takes-all inspired network structure can be employed to solve Sudoku puzzles on three diverse hardware accelerators. By exploring several network implementations, we measured the number of solved puzzles in a set of 100 assorted Sudokus, as well as time and energy to solution. Concerning the last two indicators, our measurements indicate that it can be beneficial to port a network to an analogue hardware system.
The overwhelming majority of High Performance Computing (HPC) systems and server infrastructure uses Intel x86 processors. This makes an architectural analysis of these processors relevant for a wide audience of administrators and performance engineers. In this paper, we describe the effects of hardware controlled energy efficiency features for the Intel Skylake-SP processor. Due to the prolonged micro-architecture cycles, which extend the previous Tick-Tock scheme by Intel, our findings will also be relevant for succeeding architectures. The findings of this paper include the following: C-state latencies increased significantly over the Haswell-EP processor generation. The mechanism that controls the uncore frequency has a latency of approximately 10 ms and it is not possible to truly fix the uncore frequency to a specific level. The out-of-order throttling for workloads using 512 bit wide vectors also occurs at low processor frequencies. Data has a significant impact on processor power consumption which causes a large error in energy models relying only on instructions.
Many complex problems, such as natural language processing or visual object detection, are solved using deep learning. However, efficient training of complex deep convolutional neural networks for large data sets is computationally demanding and requires parallel computing resources. In this paper, we present two parameterized performance models for estimation of execution time of training convolutional neural networks on the Intel many integrated core architecture. While for the first performance model we minimally use measurement techniques for parameter value estimation, in the second model we estimate more parameters based on measurements. We evaluate the prediction accuracy of performance models in the context of training three different convolutional neural network architectures on the Intel Xeon Phi. The achieved average performance prediction accuracy is about 15% for the first model and 11% for second model.
System self-tuning is a crucial task to lower the energy consumption of computers. Traditional approaches decrease the processor frequency in idle or synchronisation periods. However, in High-Performance Computing (HPC) this is not sufficient: if the executed code is load balanced, there are neither idle nor synchronisation phases that can be exploited. Therefore, alternative self-tuning approaches are needed, which allow exploiting different compute characteristics of HPC programs. The novel notion of application regions based on function call stacks, introduced in the Horizon 2020 Project READEX, allows us to define such a self-tuning approach. In this paper, we combine these regions with the Q-Learning typical state-action maps, which save information about available states, possible actions to take, and the expected rewards. By exploiting the existing processor power interface, we are able to provide direct feedback to the learning process. This approach allows us to save up to 15% energy, while only adding a minor runtime overhead.
Scientific applications often contain large and computationally intensive parallel loops. Dynamic loop self scheduling (DLS) is used to achieve a balanced load execution of such applications on high performance computing (HPC) systems. Large HPC systems are vulnerable to processors or node failures and perturbations in the availability of resources. Most self-scheduling approaches do not consider fault-tolerant scheduling or depend on failure or perturbation detection and react by rescheduling failed tasks. In this work, a robust dynamic load balancing (rDLB) approach is proposed for the robust self scheduling of independent tasks. The proposed approach is proactive and does not depend on failure or perturbation detection. The theoretical analysis of the proposed approach shows that it is linearly scalable and its cost decrease quadratically by increasing the system size. rDLB is integrated into an MPI DLS library to evaluate its performance experimentally with two computationally intensive scientific applications. Results show that rDLB enables the tolerance of up to (P minus one) processor failures, where P is the number of processors executing an application. In the presence of perturbations, rDLB boosted the robustness of DLS techniques up to 30 times and decreased application execution time up to 7 times compared to their counterparts without rDLB.
Since quantum computers will be able to break all public-key encryption schemes employed today efficiently, quantum-safe cryptographic alternatives are required. One group of candidates are lattice-based schemes since they are efficient and versatile. To make them practical, their security level must be assessed on classical HPC systems in order to determine efficient but secure parameterization.In this paper, we propose a novel parallelization strategy for the open source framework p3Enum which is designed to solve the important lattice problem of finding the shortest non-zero vector in a lattice (SVP). We also present the p3Enum extreme pruning function generator (p3Enum-epfg) which generates optimized extreme pruning functions for p3Enum's pruned lattice enumeration by employing a parallelized simulated annealing approach. We demonstrate the quality of the pruning functions delivered. Combining the new parallelization with optimized pruning functions speeds up p3Enum by a factor up to 3 compared to the previous version.Additionally, we compare the required runtime to solve the SVPs with state-of-the art tools and, for the first time, also visualize the statistical effects in the runtime of the algorithms under consideration. This allows a considerably better understanding of the behavior of the implementations than previous average-value considerations and demonstrates the relative stability of p3Enum's parallel runtimes which improve reproducibility and predictability. All these advancements make it the fastest SVP solver for lattice dimensions 66 to 92 and a suitable building block as SVP-oracle in lattice basis reduction.
Detecting performance anomalies and taking corrective or preventive actions are key requirements in high-performance software systems. However, progress in research related to performance anomaly detection has been limited due to the lack of publicly available datasets. This holds true for performance anomaly detection in API gateways as well. With the advent of the API Economy, API gateways are likely to be widely deployed, thus becoming a key component of enterprise integration architectures. Therefore, it is important to detect performance anomalies in such high-performance API-Gateway systems. The primary contribution of the paper is Vichalana, a dataset that can be used to evaluate the accuracy of anomaly detection algorithms in API-Gateways. In order to generate this data set we first classify the anomalies in API-Gateways into 7 types. Second, we provide detailed criteria for re-creating them in API-Gateway environments. Third, we re-create these anomaly types in an API-Gateway environment (similar to a production environment) and collect 25 measurement parameters relating to CPU, memory, network IO and disk IO under both normal and anomalous conditions. The data set we provide is based on the data we collect in these tests. Finally, using several example scenarios, we illustrate the behaviour of several measurement parameters under different anomaly types. We provide the reasoning for particular behaviours of parameters for different types of anomalous behaviours.
We investigate the usage of short video datasets in place of large image datasets for outfit transfer. We replicate the warp stage of prior work, SwapNet, while swapping out the 800K-image DeepFashion dataset for two 5-minute videos. By successfully training the warp stage on video, we show that the previously proposed transfer technique for images has potential to apply to subjects in motion. In addition, specifically for video applications, we show the model need not be trained on a comprehensive dataset; instead the model only needs videos for the source outfit and target subject. Our results show promise for the usage of video datasets in future work to achieve fully-textured outfit transfer. We expect the implications of convenient-to-collect video datasets to appeal to small companies that lack resources to collect and annotate big data. If combined with high performance computing, faster training times in the cloud could lead to frictionless user experiences.
Graph partitioning is a common computational phase in many application domains, including social network analysis, data mining, scheduling, and VLSI design. The significant SIMT compute power of a GPU makes it an appropriate platform to exploit data parallelism in graph partitioning and accelerate the computation. However, irregular, non-uniform, and data-dependent graph partitioning sub-tasks pose multiple challenges for efficient GPU utilization. Some of these challenges include load imbalance, non-coalesced memory accesses, and warp execution inefficiency. In this paper, we describe an effective and methodological approach to enable multi-level graph partitioning on GPUs. Our solution avoids thread divergence and balances the load over GPU threads by dynamically assigning appropriate number of threads to process the graph vertices and their irregular sized neighbors. Our design is autonomous, i.e., all the steps are carried out by the GPU with minimal CPU involvement, which is required for a range of GPU applications as a pre-processing step. We show that our approach performs better and is comparable in partitioning quality with respect to the state-of-the-art CPU-based parallel graph partitioner (mtmetis). Moreover, to the best of our knowledge, it is the first autonomous approach on GPU.
The continuous innovations in both high-end mobile devices and wireless communication technologies, fueled by the growing interest of mobile device users, have driven the latest development of mobile 3D video services. One of the critical challenges for mobile 3D video delivery is the limited bandwidth provided by the wireless communications between mobile devices. Nowadays, network operators are trying to cope with significant increase of data traffic amount and adopt diverse solutions to expand their network capacity. Among long-term solutions is network convergence, which involves close interworking of existing 2.5G/3G/4G networks with the new generation networks in terms of handover, network selection and network integration with other networks (e.g., WLAN, terrestrial microwave network, satellite network, etc.). In this context, the diversification in mobile devices and heterogeneity of the wireless environment make provision of always best connectivity of mobile users a challenge for the service providers. This paper proposes RA3D, a reputation-based adaptive 3D video delivery solution in heterogeneous wireless networks, which supports Always Best Experience to the mobile users by making use of multipath content delivery technologies.
In order to solve many real problems, we have to sort array segments of data. This sorting task is called segmented sorting. Problems like image processing and suffix array construction usually have huge amount of data and their solutions make use the segmented sorting procedure. There are several techniques for solving the segmented sorting. A previous work showed that a strategy called fix sort had a good performance to sort segments of arrays. This strategy adjusts the input array to allow off-the-shelf general sorting algorithms to execute segmented sorting. Besides the extensive tests that were done in the previous work, the implemented fix sort solution did not explore in full the proposed parallel algorithm. In this work we revisit the sequential and parallel algorithms to the fix sort strategy creating new parallel and sequential implementations. We compared our results with the previous methods to sort multiple segments. The obtained results showed that our implementations of fix sort strategy achieved better execution times than the previous ones.
Pseudo-Random Number Generators (PRNG) are omnipresent in computer science: they are embedded in all approaches of numerical simulation (for exhaustiveness), optimization (to discover new solutions), testing (to detect bugs) cryptography (to generate keys), and deep learning (for initialization, to allow generalizations)…. PRNGs can be basically divided in two main categories: fast ones, robust ones. The former have often statistical biases such as not being uniformly distributed in all dimensions, having a too short period of time,…. In the latter case, statistical quality is present but the generators are not fast. This is typically what is encountered when running a cryptographically secure PRNG. In this paper, we propose alternative architectures, based on jumps in N-cubes, that provide fast and robust PRNGs for efficient simulations, but not exclusively for that.
Today's society faces an unprecedented deluge of data that requires processing and analysis. Data Stream Processing (DSP) applications are often employed to extract valuable information in a timely manner as they can handle data as it is generated. The typical approach for deploying these applications explores the Cloud computing paradigm, which has limitations when data sources are geographically distributed, hence introducing high latency and achieving low processing throughput. To address these problems, current work attempts to take the computation closer to the edges of the Internet, exploring Fog computing. The effective adoption of this approach is achieved with proper throughput modeling that accounts for characteristics of the DSP application and Fog infrastructure, including the location of devices, processing and bandwidth requirements of the application, as well as selectivity and parallelism level of operators. In this work, we propose a throughput model for DSP applications embracing these characteristics. Results show that the model estimates the application throughput with less than 1% error.
Air pollution is a severe issue in many big cities due to population growth and the rapid development of the economy and industry. This leads to the proliferating need to monitor urban air quality to avoid personal exposure and to make savvy decisions on managing the environment. In the last decades, the Internet of Things (IoT) is increasingly being applied to environmental challenges, including air quality monitoring and visualization. In this paper, we present CAVisAP, a context-aware system for outdoor air pollution visualization with IoT platforms. The system aims to provide context-aware visualization of three air pollutants such as nitrogen dioxide (NO 2 ), ozone (O 3 ) and particulate matter (PM 2.5 ) in the city of Melbourne, Australia. In addition to the primary context as location and time, CAVisAP takes into account users' pollutant sensitivity levels and color vision impairments to provide personalized pollution maps. Experiments are conducted to validate the system and results are discussed.
