Measuring a qubit state is a fundamental but error-prone task in quantum computing. As the number of qubits increases, scalable readout demands multiplexed qubit measurement, which often suffers from crosstalk and other nonidealities. The conventional approach of qubit state detection often struggles with scalability and noise resilience. Neural network (NN)-based discriminators have emerged as a promising alternative, offering superior performance for inferring qubit states from multiplexed signals. However, their deployment on hardware platforms like Field programmable gate arrays (FPGA) is hindered by computation complexity, resource constraints, and latency. In this work, we present an end-to-end methodology for designing and deploying quantized NN-based multi-qubit state discriminators on FPGAs. We demonstrate that implementing a fully connected neural network accelerator for multiqubit readout is advantageous, balancing computational complexity with low latency requirements without significant loss in accuracy. We significantly reduce the FPGA footprint and latency of the neural network by employing quantization-aware training (QAT) to quantize weights, activations, and inputs, and leveraging automated mapping flows for efficient, hardware-aware design-space exploration and optimization. The hardware accelerator performs frequency-multiplexed readout of five superconducting qubits in 26.7 ns, on a radio frequency system on chip (RFSoC) ZCU111 FPGA. These modules can be implemented and integrated into existing FPGA based quantum control and readout platforms, making them ready for experimental deployment.
We consider area optimization of floating-point (FP) ALUs by sharing hardware among the set of supported operations and precisions. We generate combinational FP cores for individual operators using the open-source FloPoCo tool [10], and identify opportunities for hardware sharing across cores. We also consider hardware-sharing in FP ALUs that support mixed precision, namely FP32 and BF16 (brain-float 16-bit format). We implement the FP ALUs in 45nm standard cells, and optimize their performance using retiming. For FP ALUs operable over 600 MHz, we achieve 14.5% area reduction vs. baseline FP ALUs without the proposed hardware-sharing optimizations. We also estimate the overall area impact of incorporating the optimized FP ALUs into an elastic coarse-grained reconfigurable array (CGRA) [3], achieving between 8-9.5% area savings.
Hyperspectral imaging (HSI) enables precise intraoperative brain tumor detection by capturing high-dimensional spectral information that distinguishes malignant from healthy tissue. However, processing HSI datacubes in real time poses significant challenges under the strict power, latency, and sterility constraints of surgical environments. This work-in-progress paper presents a proposal for a heterogeneous, end-to-end hardware-accelerated HSI pipeline on the AMD Versal Adaptive Compute Acceleration Platform (ACAP), integrating calibration, normalization, PCA-based spectral reduction, U-Net segmentation, and real-time rendering across the programmable logic (PL), AI Engine (AIE) array, and processing system. The segmentation stage is fully implemented using a DPU-accelerated U-Net on 15 PCA-reduced bands, achieving 291 FPS and 3.44 ms latency at 17.36W on the VCK190, representing a 14.6x energy efficiency gain over an RTX 5080 GPU, while maintaining 0.9767 accuracy and 0.8521 Dice score. This work demonstrates a viable path toward a fully integrated, single-chip HSI surgical guidance system for real-time intraoperative brain tumor detection.
Phylogenetics study the evolutionary relationships of organisms through an iterative process of creating and evaluating tree topologies. This process is highly compute-intensive; creating a large phylogenetic tree requires hundreds to thousands of CPU hours. Most phylogenetic analyses use the Phylogenetic Likelihood Function (PLF) to evaluate trees; it accounts for 85%-95% of the total analysis time. We present the first, to our knowledge, implementation of a protein-based PLF accelerator on the AMD Versal Adaptive SoC; it achieves 2.5x higher FLOPS performance than a DNA-based Versal accelerator, and up to 7.2x faster execution than the AVX2 PLF implementation in RAxML (a widely used, highly optimized phylogenetic software) on a single x86 CPU core. We demonstrate the potential and discuss limitations of the Versal Adaptive SoC for high-arithmetic-intensity phylogenetic workloads.
Spiking Neural Networks (SNNs) are energy-efficient algorithms that have proven effective for AI-based sensor-data processing at the edge. The new generation of high-density sensor arrays enables augmented decoding and classification capabilities for sensing devices, however, similarly to what has been observed in image processing, dense layers become impractical as the sensor array size increases, both due to the growing number of channels, which increases the memory footprint of AI models, and because they fail to capture spatial features inherently present when sensor sensing areas overlap. This paper introduces a new end-to-end spiking convolutional accelerator, designed for deployment on low-cost and low-power FPGA devices for high-count sensor data analysis. The system integrates a RISC-V softcore responsible for managing input/output dataflow, an encoding and a decoding slot for sampleto-spike data conversion and viceversa, and a programmable and sparsity-aware convolutional spiking neural network accelerator. We evaluated the system, implemented on a Lattice iCE40UP5K FPGA, on a High-Density surface EMG continuous force tracking task included in the Hyser dataset. The proposed solution achieves accuracy comparable to that of a dense baseline model, while reducing the memory footprint by a factor of 5.1x and dissipating only 35 pJ per synaptic operation, corresponding to 6.8 mW during inference.
