With the ever-increasing density of electronics, whether at a system, sub-system or device level, modelling and simulation is becoming a vital stage of the design process. The development of efficient, fast and accurate techniques is essential in delivering designs that are right first time, on time and within budget. Another significant issue for designers is the increasing complexity of systems, such as system-on-chip or complete network systems on a single chip as well as highly integrated modular systems such as mobile telecommunications, personal electronics, aerospace and automotive applications. Tools and techniques that are able to handle this level of complexity at different levels of abstraction are required to make these advanced designs possible.
Test sets consisting of incompletely specified test vectors for full-scan circuits have applications in input test data compression and power reduction. Earlier procedures for reducing the percentage of specified values in a given test set maintained the test set size. A procedure is described that starts from a given (compact) test set and reduces the percentage of specified values by replacing a selected test vector with a subset of test vectors that have fewer specified values per test vector and together detect the same subset of faults. By applying this replacement process iteratively, the procedure provides a series of solutions with increasing test set sizes and decreasing numbers of specified values per test vector. The importance of considering a series of solutions is demonstrated in the application of input test data compression.
A novel request-driven globally asynchronous locally synchronous (GALS) technique for the system integration of complex digital blocks is proposed. For this new GALS technique, an asynchronous wrapper compliant is developed and evaluated. This proposed GALS technique is applied to a baseband processor compatible with the wireless LAN standard IEEE 802.11a. The developed GALS baseband processor chip is fabricated and measured. Besides improvements of the system integration process, a 5 dB reduction in electromagnetic interference, 30% reduction in instantaneous supply current variation, and similar dynamic power consumption as in the synchronous baseband processor is achieved.
Java is widely applied in current embedded systems due to its object-oriented features and advantages such as security, robustness, and platform independence. A Java virtual machine is needed to execute Java programs. However, in most of the existing solutions to Java virtual machines, the overhead of executing object-oriented related instructions is significant and becomes the bottleneck of system performance. To solve this problem, a novel Java processor called jHISC is proposed, which mainly targets J2ME and embedded applications. In jHISC, the object-oriented related instructions are implemented by hardware directly, as a hardware-readable data structure is used to represent the object. The complete system with 4 kB instruction cache and 8 kB data cache is described by VHDL and implemented in a Xilinx Virtex FPGA. It occupies 601 859 equivalent gates and the maximum clock frequency of the system is about 30 MHz. Compared with PicoJava II, the overall performance is speeded up 1 to 7.4 times and the execution efficiency of object-oriented related bytecodes is improved by 0.91 to 13.2 times for the same clock frequency.
Thinning is a very important operation in the pre-processing stage of fingerprint recognition. With the availability of fast thinning hardware, real-time image processing applications can be achieved. The authors introduce a detailed hardware architecture design of a thinning processor used in an embedded fingerprint recognition system. The proposed thinning algorithm has a parallel-pipelining structure suited to hardware realisation, which is implemented and verified using FPGA. Equipped with a modification unit array, a designated operating schedule, and an address generator based on systolic counter, this thinning processor is able to perform a thinning operation within 0.07 s at 40 MHz for a 512 x 512 picture, which is at least 40 times faster than software execution. Consequently, the proposed thinning processor was successfully integrated into a real-time fingerprint recognition system.
