Single Pair Ethernet (SPE) standard implementations offer simplified cabling requirements tailored to specific application domains. Currently, 100BASE-T1, 10BASE-T1L, and 10BASE-T1S are the SPE standards that have gained some acceptance. Unfortunately, the time synchronization performance of SPE is in question, especially for the 10 Mb/s variants, as the Physical Layer (PHY) uses low signaling rate, complex coding, and digital signal processing; furthermore, 10BASE-T1S also offers multidrop, half-duplex communication services. Our paper introduces a modular hardware solution for SPE performance evaluation utilizing Microcontrollers (MCU) and the flexPTP MCU Precision Time Protocol (PTP) implementation. We investigate the standard 100BASE-TX Ethernet and compare it to the automotive 100BASE-T1, 10BASE-T1S, and the long-range industrial 10BASE-T1L Ethernet with a PI and a Kalman filter servo algorithm. Our investigation shows that 100BASE-T1 offers significantly better accuracy and precision than the others; 100BASE-TX follows it in performance, and the 10BASE-T1L and 10BASE-T1 offer the worst timing performance.
Neuromorphic accelerators, whether asynchronous meshes or globally-asynchronous, locally synchronous (GALS) fabrics, usually devote die area to barrier synchronizers, finely tuned clock trees, and metastability filters to keep spikes in lock-step. How much of that circuitry is truly indispensable? We quantify the intrinsic jitter tolerance of spiking neural networks (SNNs) and show how to push this tolerance further. We introduce a clock offset injector, a single GPU tensor op that time-shifts each core’s spikes by an arbitrary delay, and allows any PyTorch SNN to be stress-tested or hardened without code changes. Vision (N-MNIST) and audio (Spiking Heidelberg Digits) models, trained with and without our proposed offset-aware augmentation, are evaluated across nine skew levels (0-50% of the sample window) and up to eight cores. Baseline N-MNIST stays within ±1 percentage points (pp) until skew reaches 18 ms (6.1%). By accounting for temporally misaligned spikes during training time, we extend survival to 46 ms. Timing-critical SHD collapses beyond 23 ms (9%) but regains 6-9 pp after augmentation. These numbers map out safe envelopes for clock simplification: vision-only workloads can tolerate ≈ 3 ms per hop, while mixed vision-audio workloads must hold skew below 2 ms, or depend on timing-offset aware training. This ultimately shows how to enable lower-effort clocking and using software-level mitigation when needed.
A time transfer link consisting of PTP High Accuracy equipment (PTP-HA, e.g., White Rabbit) can transfer time with sub-nanosecond accuracy. Originally PTP-HA equipment is calibrated as a set of two devices. Progress in calibration makes exchange of individual components, such as pluggable transceivers, possible without the need for expensive in-situ end-to-end calibrations. This is expected to be covered in a future release of the IEEE 1588 standard.To determine the latencies of a pluggable transceiver, a time delay calibrated reference photodetector is essential. Latency values are stored in the transceiver memory, which enables exchange without breaking calibration.This paper describes the results of inter-comparing several calibrated reference photodetectors that were calibrated in different calibration setups. These photodetectors were exchanged between laboratories to cross-verify their stated optical to electrical time delays. The initial cross-verification results lead to further investigation of the calibration setup. The results of this investigation will be reported.
Measuring the performance of one-sided and collective operations on a set of distributed resources is not trivial because of the complexity of distributed time measurement on non-synchronized hardware. Simulation is attractive because distributed applications can be executed on a controlled set of resources and in a reproducible manner. Writing a fully calibrated simulator for a new software library represents however a time- and labor-intensive effort that is usually only undertaken for well established software solutions such as the MPI standard.This paper introduces an approach leveraging the SimGrid simulation framework for the study of an existing standard for high-performance computing parallel applications, featuring one-sided communications and atomic and collective operations. We present the several mechanisms that are mandatory to integrate the behavior of the real distributed applications into the simulated platform. Leveraging this simulation framework greatly simplifies this endeavor, opening the way to the study of more distributed middleware and libraries through realistic simulations.
IEEE 802.1AS and time-sensitive networks are becoming increasingly widespread and serve as the basis for scheduled traffic or sequence of events in industrial networks. The moment a fault occurs in a TSN network, troubleshooting is laborious and expensive. To mitigate the expenses and duration of troubleshooting, it is imperative to implement monitoring, fault detection and diagnosis, and root cause analysis. Decentralized expert knowledge is the sole source of information regarding symptoms, potential faults, and causes. Knowledge graphs are used in various disciplines, including network troubleshooting, to share knowledge of specific domains. At present, there is no methodical troubleshooting assistant for IEEE 802.1AS. The current methods for monitoring, diagnosis, and fault analysis in networks and time synchronization are comprehensively examined in this paper. In addition, it gives an ontology, possible symptoms, faults, and root causes, as well as an IEEE 802.1AS knowledge graph for fixing problems. A test setup is then used to implement and assess the knowledge graph that has been created. This work establishes the foundation for a shared knowledge base for root-cause analysis in IEEE 802.1AS networks, which requires further development to minimize the time and expenses associated with troubleshooting.
