Aiming at the efficient radiation simulation of anten-nas with dielectric slabs and spatial multiscale features, a discon-tinuous Galerkin (DG) scheme for the multi-region surface inte-gral equation is presented in this letter. Boundary lines between different materials can be handled independently without merging and reducing unknowns at the junction, which simplifies the cal-culation. Numerical experiments of different kinds of antennas are carried out to verify the accuracy and efficiency of the proposed method through comparisons.
Dual-circularly-polarized magneto-electric(ME) dipole for satellite system is proposed in the paper. The results indicate the design has the excellent results. The impedance bandwidth of the antenna is 10.7-14.9GHz, and the antenna's axial ratio bandwidth is about 32.8%. The results indicate that both polars have similar performance. The antenna has a size of 10.3mm*10.3mm*3.4mm, which is suitable for implementations in phased array. In order to improve performance of the antenna, the wide-angle impedance matching(WAIM) layer is used. Air hole is punched all around the WAIM in order to improve isolation between elements in the array.
A dual-band and dual-polarized antenna using metasurface for 5G application is proposed in this paper. The antenna has achieved excellent dual-band broadside radiation performance maintaining a low profile characteristic by introducing a dual-layer metasurface structure. The bandwidths of the proposed antenna are 13.9% (2.46-2.83GHz) and 14.4% (3.22-3.72GHz), whose overall size is 0.82λ0 × 0.82λ 0× 0.053λ0. For these dual operating bands, the antenna achieves high realized gains of 8.4-9.88dBi and 9.12-11.85dBi, respectively, with interport isolation over 40dB.
This paper proposes a 59–65 GHz, 10.58 % tuning range, -97.2 dBc/Hz@lMHz phase noise, 16 mW power consumption, 181.45 dBc/Hz@lMHz $\text{FoM}_{\mathrm{T}}$ , 0.052 mm 2 area frequency generator based on 20 GHz VCO and multiplied-by-three frequency multiplier with the technology of 40-nm and 1.1 V supply voltage. The major idea is to construct a 20 GHz VCO with good phase noise and use the theory of injection lock to attain 60 GHz output. Switching capacitors and stacked MOSFETs are used in VCO, and a fourth-order resonator is applied in the multiplier.
This paper presents an ultra-low power quartz crystal temperature-compensated real-time clock. By using a pulse injection oscillator (PIO) instead of a conventional Pierce oscillator, a multi-phase output is provided to improve digital compensation accuracy while reducing power consumption. The temperature compensation is achieved by dynamically selecting the multi-phase output of the PIO based on the lookup table data to offset the temperature drift, which improves the instantaneous compensation accuracy compared to the traditional digital frequency division-based method. An on-chip ring oscillator controlled by a proportional to absolute temperature current source using switched capacitor is implemented to obtain temperature information by counting its output frequency. Simulation based on the TSMC 65 nm CMOS process shows that the circuit has an absolute long-term compensation accuracy of 2.2 ppm and a total power consumption of 20.9 nW at typical operating conditions of 25°C and 0.6 V supply.
