To address the problem that back propagation (BP) neural networks are prone to overfitting and falling into local optimality, resulting in low accuracy of electricity load forecasting, this paper proposes a method for electricity load forecasting based on an improved genetic algorithm (GA) and the BP neural network. Through modelling and analysis of load data, better root mean square error (RMSE) and mean absolute percentage error (MAPE) are obtained compared with the traditional BP neural networks, proving the method's superiority.
Over the past few years, lightweight cryptography has been recognised as top-notch for gratifying the requirements of resource-constrained environments (RCE) for Internet of Things (IoT) applications. For several RCE applications, a range of light-weight cryptographic methods have been put forth. In this paper, the Midori lightweight block cipher has been area optimised using unconventional serial architectures and memory address scheduling techniques. This paper suggests two serial architectures for area optimisation of 64-bit and 128-bit block sizes, respectively. The proposed designs are implemented in verilog hardware description language (HDL) using the Xilinx ISE Design suite. A fair comparison of the proposed designs has been done on different families of field programmable gate array (FPGA). The proposed design has shown a percentage improvement of 22.03% and 15.28% in terms of area for 64-bit and 128-bit block size, respectively. Similarly, the percentage improvement for throughput is 21.43% and 15.65% for 64-bit and 128-bit block size, respectively on FPGA Virtex-5 platform.
The Internet of Things (IoT) is referred to as the next social application era, with its users and applications growing at an exponential rate. As technology advances, modern applications require optimised requirements such as low area, low power, and low cost, among others. Cryptography fails to meet the above-limited resource criteria, paving the way for lightweight cryptography, which deals with modern limited resource issues very efficiently. This paper discusses the lightweight shadow block cipher, which uses a generalised Feistel structure for encryption. A 4-Clock Loop Unrolled architecture (S1) of Shadow-32 and Pipelined architecture of Shadow-64 (S2) are proposed to improve the algorithm's performance, i.e., by increasing throughput and frequency. The performance metrics are compared to various lightweight block ciphers, with the best improvements in throughput of 365.6% and 140% over conventional architectures in S1 and S2, respectively.
To plan an efficient picking path for warehouse robots, a chaotic genetic algorithm with polynomial mutation is recommended in this paper. First, in order to improve the efficiency of the genetic algorithm, the chaotic theory is employed to design a population initialisation strategy, which can increase the diversity of the initial population. Second, on the basis of the mutation operator designed based on polynomial mutation, the algorithm's capacity for diversity preservation can be enhanced. Third, two novel adaptive adjustments are presented for crossover and mutation operations in order to achieve a balance between convergence and diversity. As assessment indices of the fitness function, the path length, turn timings, and running energy consumption of the robot are taken into considerations. Simulation results indicate that the suggested approach outperforms the basic genetic algorithm and the ant colony optimisation algorithm in terms of path length and energy consumption.
There is a lot of increase in technology. As there are restrictions on the resources available, there is a need to implement lightweight stream ciphers. The ciphers are used for the encryption of data. So, the security of data is also an important factor. As handheld devices are increasing, the need for energy-efficient devices becomes more vital. Keeping all these requirements in mind, researchers have done much research on ciphers. The unrolling of stream ciphers showed the energy-efficient way to implement ciphers. In this paper, the unrolling of Fruit-v2, Fruit-80 and Grain128AEAD stream ciphers is discussed. Using Xilinx ISE Design Suite and Verilog HDL, simulation is performed for different unrolling factors. Using the Synopsys DC compiler, power and energy are calculated. The unrolling rounds for which the energy is optimised for Fruit-v2, Fruit-80 and Grain128AEAD are 16, 16, and 64, respectively. This paper discusses area, power and energy consumption.
The internet of things (IoT) has recently expanded, resulting in a new world of smart gadgets with substantial security consequences. For their vital security role, lightweight block ciphers have gained a significant amount of development in low resource devices (LRDs). SIMECK is a new lightweight block cipher family that incorporates the finest aspect of both SIMON and SPECK. SIMECK is a more efficient block cipher than SIMON and SPECK cipher. These lightweight ciphers are especially referred to as an alternative to the AES for RCD. In this study, area optimised architecture is implemented for SIMECK lightweight block cipher with sizes: 64/128. For implementation on different platforms such as Sparton-6, Sparton-3, Virtex-7, Virtex-6, Virtex-5 and Virtex-4 FPGA are used to examine several properties such as block size, key scheduling, and throughput, among others. The proposed area optimised architecture have attained a maximum operating frequency of 496.429 MHz with 61 slices and a high throughput of 706.032 Mbps on the Virtex-7 platform.
Real-time grid analysis is made possible by the electric digital twin grid, which combines history and present data to convey system status and project future circumstances. Cooperative smart agents that can solve problems bigger than one agent's scope make up a multi-agent system (MAS). A micro-grid digital twin (MGDT) uses real-time data interchange and high-fidelity models to simulate a microgrid's operation. Hybrid energy storage systems are managed by agents who maximise renewable resources and minimise expenses. Microgrids combine sensing, control, and intelligence technology in utility networks. Plant management, communication protocols, and power system operations are all made easier with MAS-based control. For dependable microgrid operation, dispersed energy resources are coordinated by MAS. In order to handle complexity and improve resilience and control of the energy system, this study investigates the application of MAS in microgrid control. Energy management and agent communication in microgrids are the main topics of MAS research. Integrating microgrid digital twins with MAS holds promise for advancing energy systems.
The research paper presents the design methodology with novel task distribution technique on multi-processor system on chip (MPSoC) for speeding up the execution of arithmetic application. Utilisation of multiple soft core processors on field programmable gate array (FPGA) reduces the overload of adding external hardware to a system. Parallel processing of soft core processor with proposed task distribution technique makes any application to execute at faster rate. This task distribution based speed enhancement technique for arithmetic application is very feasible and appealing to the modern applications like neural networks, fuzzy logic, algorithms of machine learning etc. Experimentation on such architecture with arithmetic application shows significant increase in speed of operation with respect to conventional design. This is implemented using Microblaze soft core processor architecture on Xilinx Virtex 5 FPGA board.
The Internet of Things (IoT) is making significant progress in various fields; software-defined networks with multiple controllers have become popular because they make it easier to manage large networks. But they are open to several attacks, which makes controller topologies inconsistent. To solve this problem, we suggest a multi-controller blockchain for software-defined networking (SDN) network. This security architecture combines blockchain and multi-controller SDN and divides the network into several domains. We put forth a blockchain-based solution. This paper proposed a model blockchain-enabled SDN multi-controller architecture for IoT networks that uses a clustering algorithm and a new routing protocol that is both secure and energy-efficient. Experimental results indicate that the cluster-based routing protocol has a greater capacity, a shorter response time, and a lower overall power requirement than other protocols. It has been shown that our proposed architecture outperforms the classic blockchain.
Some of the advantages of the DC-DC converter digital control, such as programmability and improved control algorithms, have made it more popular in modern times. As a significant part of digital control, digital pulse width modulator (DPWM) is designed to fulfill number of requirements for high efficiency. The existing DPWM framework is implemented with high resolution along high switching frequency, but mandatory counter clock frequency is higher. To manipulate this drawback, the hybrid DPWM architecture is proposed that consolidates reversible synchronous sequential counter (RSSC) and synchronous phase-shifted circuit (SPS). The RSSC is employed to count trigger signal at each clock period. Whereas, SPS circuit is employed to select the clock by the quadrant phase-shifted clocks. The coding is activated in Verilog and the proposed RSSC design is synthesised utilising Xilinx ISE.
