Modern sensor networks often consist of larger numbers of mobile sensor nodes. In such sensor networks, multiple sensor nodes can measure common targets. If they measure their targets simultaneously, the impact of measurement errors can be reduced. Alternatively, if they perform their measurements at the same frequency while offsetting their measurement timings, temporal resolution can be enhanced. However, since a sensor network composed of mobile sensor nodes changes its topology dynamically, it becomes difficult to coordinate their measurement timing. In this work, we propose bio-inspired algorithms for the coordination of the measurement timing: synchronization, where both the periods and phases of sensor nodes are synchronized, and desynchronization, where their periods are synchronized but their phases are evenly offset. We evaluate our proposed synchronization method for these algorithms through a simulation.
AI-based traffic classification is crucial for optimizing resource allocation and threat detection in networks, particularly in resource-constrained IoT environments where traditional methods are inadequate. However, deploying large machine learning (ML) and deep learning (DL) models in such environments poses significant challenges due to their high computational requirements and storage needs, which can lead to inefficiencies and scalability issues. This paper introduces novel model optimization techniques-Min-BitNet and SlimMatrixNet-to overcome these limitations and replace state-of-the-art TinyML-based approaches. These models significantly reduce size while maintaining high accuracy: Min-BitNet achieves 99.46% and SlimMatrixNet achieves $\mathbf{9 6. 3 7 \%}$, compared to $\mathbf{9 9. 9 6 \%}$ for the uncompressed model. Validated through OMNeT++ simulations and hardware implementations, SlimMatrixNet offers superior performance in accuracy, size, and delay, providing an efficient IoT anomaly detection solution without compromising accuracy.
Federated learning (FL) offers a promising approach to improving the efficiency and privacy of Internet of Things (IoT) systems, particularly in environments where data is distributed across numerous devices. However, challenges remain in selecting the right FL model for specific applications, managing data privacy, and optimizing system performance. This paper evaluates four FL models - FedAvg, FedPer, FedProx, and FedSGD - against these challenges, focusing on their ability to optimize resource management, enhance data privacy, and reduce communication costs in real-time IoT settings. We provide a detailed comparison of their loss rates, execution times, and scalability, offering valuable insights into how each model performs under varying conditions. By addressing these key issues, our work contributes to the effective deployment of FL in distributed IoT systems, guiding the selection of the most suitable model for diverse applications.
This work presents a new reproducible test framework for Organic Computing (OC) applications in autonomous driving. We solve two major problems in performing reproducible experiments. First, we demonstrate a simple and inexpensive approach to recreate a test environment within the CARLA simulator to investigate accidents in depth as close to the real environment as possible. Secondly, we implement a new script-based framework to control mechanisms for generating repeatable experiments, ensuring consistent experimental results and verifying accurate trajectories.
Field-Programmable Gate Arrays (FPGAs) are increasingly used in critical applications and as versatile platforms for research, prototyping, and education. Their reprogrammable nature, however, makes them vulnerable to security threats, particularly through bitstream vulnerabilities. This paper presents a new approach for the real-time detection and mitigation of such vulnerabilities. We introduce BitVulLLM, a fine-tuned variant of LLAMA2 specifically used for FPGA bitstream vulnerability detection. As part of this research, we generated a comprehensive dataset of FPGA bitstreams, including secure and vulnerable configurations, to address the challenges of detecting and rectifying security flaws. Our method not only identifies vulnerabilities with high precision, but also generates secure bitstreams, significantly bolstering the security of embedded systems. This research represents a significant advancement in safeguarding FPGA applications and other use cases from cyber threats, improving the overall performance and reliability of embedded systems and hardware security.
