Deterministic Synchronous Multichannel Extension (DSME) is a prominent MAC behavior first introduced in IEEE 802.15.4e supporting deterministic guarantees using its multisuperframe structure. DSME also facilitates techniques like multi-channel and Contention Access Period (CAP) reduction to increase the number of available guaranteed timeslots in a network. However, any tuning of these functionalities in dynamic scenarios is not explored in the standard. In this paper, we present a multisuperframe tuning technique called DynaMO which tunes the CAP reduction and Multisuperframe Order in an effective manner to improve flexibility and scalability, while guaranteeing bounded delay. We also provide simulations to prove that DynaMO with its dynamic tuning feature can offer up to 15--30% reduction in terms of latency in a large DSME network.
Hands-on experience is crucial to truly understanding the principles of operating systems (OS). This paper describes a preemptive, multithreaded embedded OS assigned as a project in a junior-level OS course. It targets the popular 8051 instruction set architecture (ISA) and can run with as little as 128 bytes of RAM and 1 KB of program memory with preemption and synchronization primitives such as semaphores. It is written in C and assembly and compiled using the open-source Small Device C Compiler (SDCC). It runs on the free EdSim51 simulator, which simulates common peripherals such as LCD, keypads, 7-segment LEDs, ADC, and UART all in high fidelity. This course project has received positive feedback from students who took the course.
Industrial process control systems are time-critical systems where reliable communications between sensors and actuators need to be guaranteed within strict deadlines to maintain safe operation of all the components of the system. WirelessHART is the most widely adopted standard which serves as the medium of communication in industrial setups due to its support for Time Division Multiple Access (TDMA) based communication, multiple channels, channel hopping, centralized architecture, redundant routes and avoidance of spatial re-use of channels. However, the communication schedule in WirelessHART network is decided by a centralized network manager at the time of network initialization and the same communication schedule repeats every hyper-period. Due to predictability in the time slots of the communication schedule, these systems are vulnerable to timing attacks which eventually can disrupt the safety of the system. In this work, we present a moving target defense mechanism, the SlotSwapper, which uses schedule randomization techniques to randomize the time slots over a hyper-period schedule, while still preserving all the feasibility constraints of a real-time WirelessHART network and makes the schedule uncertain every hyper-period. We tested the feasibility of the generated schedules on random topologies with 100 simulated motes in Cooja simulator. We use schedule entropy to measure the confidentiality of our algorithm in terms of randomness in the time slots of the generated schedules.
Virtualization is the main building block of many architectures and systems from embedded computing to large scale data-centers. Managing efficiently computing resources and their power consumption becomes fundamental to optimize the performance of the workloads running on those systems, however, hardware tools like Intel RAPL can only introduce power caps without considering performance. This paper presents a performance-aware power capping orchestrator for the Xen hypervisor. The tool exploits hybrid power management techniques to minimize power consumption respecting a given SLA, leveraging RAPL and overcoming its limitations. Experimental evaluation shows that the proposed approach guarantees good results for almost all the analyzed benchmarks (e.g. CPU-, memory- and IO-bound).
Some of the most recent applications and services revolve around the analysis of time-series, which generally exhibits chaotic characteristics. This behavior brought back the necessity to simplify their representation to discover meaningful patterns and extract information efficiently. Furthermore, recent trends show how computation is moving back from the Cloud to the Edge of network, meaning that algorithms should be compatible with low-power embedded devices. A family of methods called Symbolic Analysis (SA) tries to solve this issue, reducing the dimensionality of the original data in a set of symbolic words and providing distance metrics for the obtained symbols. However, SA is usually implemented using application-specific tools, which are not easily adaptable, or mathematical environments (e.g. R, Julia) that do not ensure portability, or that require additional work to maximize computing performance. We propose here SAGe: a code generation tool that helps the user to prototype efficient and portable code, starting from a high-level representation of SA requirements. Other than exploiting similarities between SA pipelines, SAGe employs general code templates to build and deploy the code on different architectures, such as embedded devices, microcontrollers, and FPGAs. Preliminary results show a speedup up to 223x against Python implementations running on an x86 desktop machine and a notable increase in computational efficiency on a reconfigurable device.
