This paper studies large-scale OCR processing as a parallel-systems design problem and shows that high-throughput document processing is attainable on a single high-end workstation using open-source OCR components, reducing reliance on per-page cloud OCR services. We present three parallel architectures for massive PDF document processing: (1) a Ray-based distributed pipeline with integrated RAG capabilities achieving 24.3 × speedup with fault tolerance, (2) a local multi-process architecture using ProcessPoolExecutor that achieves 69.9 × speedup—reducing processing time from 5 hours to 4.3 minutes for 11,368 pages, and (3) a hybrid design combining Ray orchestration with optimized local workers whose multi-GPU scaling is an analytical projection (estimated 199 × , ∼ 1.5 minutes, with three GPUs). Experiments on banking documents using an Intel Core i9 with dual RTX 4090 GPUs report efficiency values exceeding 100% in CPU+GPU configurations (up to 1,531% when the efficiency denominator excludes the GPU). Quality evaluation against a commercial reference (Azure Document Intelligence) establishes a 24.78% Character Error Rate for the open-source OCR pipeline (PaddleOCR + fuzzy reconstruction), quantifying the speed–quality trade-off between 100 DPI and 300 DPI processing. A comparative retrieval evaluation indicates that this character-level degradation does not impair semantic retrieval in the tested setup. These results suggest that organizations can reduce per-page cloud OCR cost and vendor dependency for high-throughput workloads, with quality sufficient for semantic retrieval and RAG-based tasks. For accuracy-critical applications (legal, medical, archival), the 300 DPI architecture maintains full fidelity, while the 100 DPI option serves high-volume batch scenarios where semantic retrieval quality outweighs character-level precision.
Microscopic traffic simulation provides detailed representations of vehicle interactions but is often computationally intensive for large-scale or high-resolution applications. This study proposes a GPU-accelerated microscopic traffic simulation framework that reformulates the Gipps’ car-following model into a pixel-based Cellular Automata (CA) representation under an Eulerian paradigm. In this framework, vehicles are represented as collections of fine-grained spatial pixels, enabling continuous car-following dynamics to be discretized and evaluated at fixed spatial locations rather than through conventional Lagrangian vehicle tracking, thereby removing vehicle-level data dependencies and enabling efficient data-parallel execution on graphics processing units (GPUs). A CUDA-based implementation is developed in which car-following computation, vehicle updating, and trajectory recording are executed as GPU kernels within a unified simulation pipeline, minimizing CPU-GPU communication overhead. Numerical experiments demonstrate that the proposed framework preserves the behavioral characteristics of the original Gipps’ model and reproduces key traffic dynamics, including free-flow and congested regimes. Performance evaluations show that the GPU implementation achieves speedups of up to 26 × compared to single-core CPU execution and exhibits linear scalability with respect to spatial and temporal resolution. Overall, the results indicate that the proposed Eulerian pixel-based formulation provides a scalable and extensible computational framework that bridges behaviorally grounded traffic modeling and high-performance parallel computing.
CICEV2025 is a high-fidelity simulator and dataset that reproduces ISO 15118 traffic among electric vehicles, charging stations, and grid servers, encompassing one benign scenario and eight variants of false-authentication attacks. The framework supports integrated simulation and detection for EV charging infrastructure by combining protocol-compliant traffic generation, system-level metric collection, and scalable deep learning-based intrusion detection. In addition to full packet captures, CICEV2025 logs lightweight CPU performance counters using perf, providing host-level context unavailable in existing benchmarks such as KDD99, UNSW-NB15, CICIoMT2024, and CIC-IIoT-2025.A deep neural network is trained for nine-class classification to distinguish between the benign scenario and eight attack variants. Hyperparameters are exhaustively explored using a memory-aware grid search across multiple GPUs. To accelerate this process, an adaptive skip-factor sampler reduces the training dataset by up to 99.5% during hyperparameter optimization while maintaining the validation-weighted F1 score within 1% of the baseline.While binary detection indicates only the presence of an intrusion, the proposed multiclass model identifies the specific attack variant, enabling context-aware mitigation and targeted forensic responses in real-world EV charging environments.The proposed pipeline achieves multiclass F1 scores of up to 0.87 on CICEV2025, 0.99 on KDD99, and 0.85 on UNSW-NB15, along with 0.99 accuracy on both CICIoMT2024 and CIC-IIoT-2025. In binary mode, F1 scores range from 0.93 to 0.99 across all benchmarks, with both CICEV2025 and KDD99 achieving the maximum score. These results demonstrate that realistic EV charging attacks can be accurately and robustly detected, even after aggressive data reduction. Furthermore, the developed multi-GPU optimization pipeline delivers significant speedups, paving the way for large-scale, real-time deployment in modern electric vehicle infrastructures.
Auditability enables tracking of all read operations performed on a register, allowing data owners to monitor access to their data. This paper explores formal models of single-writer auditable registers and examines their feasibility and synchronization requirements.A natural definition of auditable registers, atomic audit, requires that all write, read, and audit operations be linearized. We show that atomic auditing is a powerful synchronization primitive, as it can be used to solve consensus. The ability to solve consensus with atomic audit depends on the number of readers and auditors: if there is a single reader or a single auditor (the writer), consensus can be solved among two processes. If there are n readers and n auditors, consensus can be solved among n processes. This result highlights the strong synchronization needed to support atomic auditing.We present wait-free implementations of single-writer atomic registers with atomic audit. For multiple readers and a single auditor, our implementation relies on primitives with consensus number 2 (e.g., swap and test&set). When there are n readers and multiple auditors, we introduce an implementation based on (n+1)-sliding registers, which have consensus number n+1.Due to the inherent complexity of atomic auditing, we introduce a weaker definition: regular audit, where audit operations are not linearized with reads and writes. We prove that atomic registers with regular audit can be implemented using standard atomic registers, demonstrating that auditability can be achieved with lower synchronization costs in this weaker model.
As Large Language Models (LLMs) continue to scale in size and complexity, their inference presents significant challenges in terms of computation, memory bandwidth, and power consumption. While GPUs have been the dominant platform for LLM inference due to their high parallelism and mature software ecosystem, they often struggle to achieve low latency in batch-one inference tasks. FPGAs, on the other hand, excel in such scenarios, as the reconfigurable architecture allows efficient design for specific workloads, enabling fine-grained parallelism and dedicated dataflows. This survey presents a comprehensive analysis of FPGA-based accelerator frameworks for LLM inference. Understanding the design principles and optimization techniques behind these frameworks is crucial for developing more effective FPGA-based accelerators. We examine how the key components of Transformer-based models—such as multi-head attention (MHA), feedforward networks (FFNs), and LayerNorm—are mapped onto hardware and how the memory bottlenecks are addressed. We also highlight some common optimization methods as well as unique design choices tailored to different application scenarios. At the end, we compare these FPGA-based solutions to GPU-based approaches and provide insights into the future directions of FPGA-based LLM acceleration.
This study proposes a Quantum Resilient Cryptographic Architecture (QRCA) to secure cloud environments against growing quantum computing threats. The architecture combines post-quantum cryptography, deep learning-based vulnerability detection, and intelligent key lifecycle management. A hybrid Quantum Bidirectional Gated Convolutional Network (QBiGCNet) model, combining Bidirectional Gated Recurrent Unit (BiGRU) and Graph Convolutional Network (GCN), identifies quantum-vulnerable patterns in classical cryptographic systems such as RSA, ECC, and AES. Based on detected vulnerabilities, post-quantum algorithms including CRYSTALS-Kyber, SPHINCS+, and Rainbow are dynamically deployed and optimized using Improved Golden Jackal Optimization (IGJO). Secure key distribution is achieved through a hybrid Attribute-Based Encryption-Quantum Key Distribution (ABE-QKD) mechanism. SHAP-based explainability provides continuous threat monitoring. The framework was evaluated using synthetically generated datasets of cloud communication telemetry and simulated quantum attack traces using Qiskit. Experimental results show that the proposed system achieves 98.6% detection accuracy, a Quantum Resilience Index (QRI) of 0.96, a latency of 29.4 ms, a throughput of 520 Mbps, and a False Positive Rate (FPR) of 2.1%, outperforming baseline security models. These results show that QRCA provides an efficient and scalable architecture for quantum-resilient security in cloud-native infrastructures.
Serverless applications typically follow a three-level hierarchy of workflows, tasks, and functions. Cloud-edge collaborative platforms efficiently execute such workflows through lightweight containers and fine-grained Function-as-a-Service (FaaS). Functions serve as the fundamental execution units and require effective scheduling to meet workflow response requirements and ensure user satisfaction. However, scheduling faces significant challenges due to stochastic workflow arrivals, complex task dependencies, parallel function execution, heterogeneous resource demands, and geographically distributed cloud-edge resources. In this paper, we propose an adaptive user-satisfaction-driven heuristic scheduling algorithm (AUHS) to maximize the mean user satisfaction (MUS) across all workflows. AUHS incorporates a cross-workflow iterative sorting mechanism to determine the batch-level optimal scheduling sequences for functions. The optimal scheduling plan of each function is automatically identified at runtime through an end-to-end non-execution latency-driven heuristic, which specifies the offloading location and execution container. AUHS is evaluated on a comprehensive set of random instances synthesized from real-world data. Experimental results show that AUHS outperforms the comparison algorithms in improving MUS by at least 4.60%, deadline satisfaction ratio by at least 15.14%, and scheduling efficiency by at least 10.13%, while reducing mean tardiness by at least 18.92%.
Quantum computing is increasingly accessed through cloud-based hybrid environments, but practical adoption depends on more than exposing remote quantum backends. It also requires managed abstractions for orchestrating classical and quantum stages, handling queues, binding backends, and integrating surrounding workflow logic. This paper presents a comprehensive survey of Quantum Serverless from that perspective. Our contribution is twofold: (1) we consolidate the key architectural components of Quantum Serverless into a unified reference architecture; and (2) we evaluate current industry and research offerings through a KPI-driven framework covering ecosystem coverage, service operability, queue handling, pricing flexibility, near-real-time readiness, and production maturity. Using this framework, we analyze 18 quantum cloud platforms and show that the ecosystem is growing but remains unevenly mature. Queue-based execution is already a baseline capability, whereas stronger serverless characteristics, such as Function-as-a-Service, Containers-as-a-Service, near-real-time responsiveness, and production readiness, remain limited. Overall, current Quantum Serverless is best understood as a queue-driven hybrid orchestration model rather than a fully mature cloud-native serverless layer. The survey identifies the main maturity gaps and outlines directions for future development.
Deep Learning Training (DLT) jobs have become the major workload in cloud GPU clusters. As an increasing variety of distinctly different DLT jobs are trained simultaneously on clusters and these jobs adopt different parallelism strategies, the challenge lies in how to schedule these jobs to efficiently utilize cluster resources considering their communication patterns. In this paper, we introduce Jaca, a job scheduler aiming to reduce Job Completion Time (JCT) by selecting the job with the highest affinity-a metric we define to reflect how efficiently a job can run on the current cluster-based on jobs' communication patterns and current cluster loads. To efficiently calculate the affinity within a reasonable time, we group the machines of the cluster, sample and prune placement orders to reduce the exploded placements plan space. This approach comprehensively considers the impact on the cluster, ultimately scheduling jobs along with their placement. Evaluation on a 12-GPU cluster demonstrates that Jaca improves the average JCT by 1.40 & times;similar to 2.82 & times;. The large-scale trace-based simulation further demonstrates that Jaca improves average JCT by up to 1.45 & times;similar to 2.40 & times; compared with the traditional job schedulers like RL-Hybrid, Yarn, Tiresias, and Gandiva.
The escalating computational demands of modern real-time systems necessitate the deployment of complex tionalities on multi-core platforms. In these environments, applications are increasingly modeled as Directed Acyclic Task Graphs (DTGs) to capture intricate execution dependencies and inherent parallelism. While existing heuristic-based scheduling schemes provide scalable solutions, they often yield sub-optimal results by satisfying only sufficient schedulability conditions. To address this efficiency gap, this work proposes an optimal, off-line scheduler synthesis strategy for multiple recurrent DTGs using the Supervisory Control of Discrete Event Systems (SCDES) framework. By modeling task execution, resource availability, and stringent timing constraints within formal "correct-by-construction" paradigm, we provide a methodology that identifies optimal schedules where traditional heuristics fail. Comparative performance evaluations demonstrate that our synthesized schedulers can successfully manage a workload approximately similar to 20% greater than current state-of-the-art heuristic methods, significantly improving resource utilization and system acceptance rates in hardware-constrained environments.
Minimizing the energy consumption of computing is essential to improve efficiency and enable further performance growth. A central point where to address this is in the scheduling of tasks onto multiprocessor systems. In many previous studies the focus of static scheduling algorithms has been on the energy consumption of the processors, where techniques like Dynamic Voltage and Frequency Scaling (DVFS) have been successfully utilized. Despite the large body of work, a notable gap exists: the energy consumed by data transfer, in particular by inter-processor communication, is neglected, even though it becomes more and more significant. To address this, we introduce a revised model that incorporates the energy costs related to task communication, combining it with the existing DVFS techniques and different static energy models. Using the proposed novel energy model, we adjust existing and propose new algorithms and study their performance as influenced by the newly introduced energy parameters. The algorithms cover both major categories, namely : list-scheduling and cluster-scheduling. Using a large set of task graphs of many different structures and sizes, and different parallel systems, our evaluation offers an extensive comparison of the algorithms and provides insights into their ability to conserve energy within the new model’s framework.
Federated learning enables collaborative model training without sharing raw data, but many practical workflows still rely on a central coordinator for client selection, update aggregation, and reward accounting. This dependence introduces trust concentration, single-point failure risks, and limited transparency in contribution assessment. This paper presents DCMF-BFL, a blockchain-assisted decentralized federated learning framework that integrates committee-based aggregation, smart-contract coordination, IPFS-backed model exchange, and contribution-aware reputation evaluation. The proposed multi-factor score is not treated as a standalone scoring novelty; instead, it is used as an interpretable reputation interface that connects accuracy improvement, gradient quality, participation recency, and verified committee service with aggregation weighting, reward or penalty accounting, and committee governance. Experiments on image, text, and tabular classification tasks under IID and non-IID partitions show that DCMF-BFL consistently improves decentralized FL performance compared with FedAvg, FedProx, and q-FFL, achieving the highest final accuracy in 14 out of 16 dataset-partition settings. Further ablation, fairness, robustness, and overhead analyses demonstrate that the integrated reputation and committee-governance design improves client-level fairness, mitigates the influence of poisoned updates, and provides auditable decentralized coordination with measurable but manageable system overhead. Overall, the results show that interpretable contribution-aware reputation can be effectively coupled with blockchain-based committee governance to support more robust, fair, and transparent decentralized federated learning.
The Internet of Things (IoT) is an advancing technology that facilitates the connection of a wide range of devices used in various aspects of daily living. In recent years, the security of IoT has become crucial because of the continuous growth of IoT devices and wireless communications. Monitoring malicious activities in IoT systems, particularly at the edge gateway, is critical to ensure security. Existing schemes for detecting malware variant traffic often fail to accurately classify variants and cannot adapt to concept drift, leaving systems vulnerable to evolving threats. To overcome these limitations, this paper introduces the Wide Slice Kronecker Network (WSliceKN) model, designed specifically to detect malware variant traffic in IoT networks. The approach begins by extracting both traffic-based and network-based features from log data, after which data augmentation is performed using an oversampling method. Afterward, malware variants are detected using WSliceKN, with concept drift monitored through an adaptive sliding window. Following drift detection, the model undergoes retraining using a combination of mutual information and a loss function. Extensive experiments are conducted, where WSliceKN outperforms existing schemes with accuracy, F1-score, recall, and precision of 94.438%, 94.622%, 95.941%, and 93.729%, respectively.
The rapid increase in the number of connected devices has created a vast computational infrastructure. While intelligent applications (e.g., VR/AR, autonomous driving, and AI assistants) demand substantial processing power, they are typically executed only in short bursts. As a result, devices remain idle for significant periods, presenting an opportunity to utilize their unused computational resources. Computation offloading has emerged as a viable solution, where resource-constrained devices leverage edge or cloud infrastructure for intensive tasks. More recently, horizontal offloading has gained attention as a complementary approach, enabling devices within the same layer to collaborate and utilize idle resources more efficiently. In this survey, we examine current research on computation offloading in collaborative computing systems that span from horizontal offloading among end devices to more complex systems involving horizontal as well as vertical offloading to edge/cloud systems. Our examination focuses on architectures, collaborative characteristics, and offloading dynamics, such as task dependency, mobility, and multi-hop offloading. We begin by introducing edge computing paradigms and key concepts in computation offloading and collaborative computing. The offloading approaches are then classified into classical, heuristic, metaheuristic, and machine learning methods, further divided into centralized, decentralized, and distributed categories. These approaches are analyzed and compared based on collaborative system, architecture, offloading dynamics, and evaluation methodology. Finally, we have identified open challenges and emphasized the need to unify research across edge computing paradigms, alongside a focus on more complex collaborative systems that resemble real-world systems, and the development of standardized evaluation frameworks as key directions for future work.
The growth in the demand for high-performance and power-efficient applications has led to an increasing interest in FPGA-based acceleration. As result, FPGAs have been applied to a wide range of applications. Still, programming them can be a complex task, requiring extensive knowledge of tools and libraries, especially in multi-FPGA architectures. As such, the desire for tools and frameworks to ease the burden and abstract the knowledge of using FPGAs has increased. OpenMP, an already dominant parallel programming model in HPC, has been shown to be a successful approach to program multi-FPGA architecture. This work is based on the OMPC-F framework, which uses the OpenMP programming model to offload computation to FPGAs. Although OMPC-F abstracts FPGA handling and task distribution from the final user, it lacks support for FPGA streaming computation. Streaming is widely used in FPGA designs to create a pipeline of computation between kernels. This work uses FPGA kernel binary information to synthesize streams as OpenMP buffers, while adapting the OpenMP dependency system accordingly. The proposal was evaluated in an AMD/Xilinx single- and multi-FPGA systems, showing speedups of the order of 6.84x in 8 FPGAs, scaling well with the addition of more kernels and FPGAs to the architecture. Moreover, compared to the regular approach to developing FPGA applications based on MPI+XRT communication, the proposed approach reduces the programming effort by 59% according to various code analysis metrics, resulting in a small average overhead of 4.3% when compared to the MPI+XRT programming model.
Collective I/Os are widely used to transform small, non-contiguous accesses into large, contiguous accesses for parallel I/O optimization. The existing collective I/O techniques were proposed with the assumption that computer memory is volatile. However, their ability is limited by the size of collective I/O buffers and communication overhead. In this paper, we propose PMIO, a novel collective I/O framework that employs node-local persistent memory on compute nodes for I/O optimization of HPC applications. First, it uses a log-structured buffer to achieve a high bandwidth of persistent memory and enforce crash consistency. Given this design, we can safely enlarge the size of collective I/O buffers without losing data when failures happen. Second, being less space-constrained than with more expensive DRAM, PMIO can buffer data across multiple collective I/O calls before writing them back to parallel file systems to further improve I/O performance. Third, we design a two-level log merging approach to reduce communication overhead for data shuffling among MPI processes on compute nodes. Our experimental results with representative MPI-IO benchmarks show that PMIO improves the I/O throughput by up to 121X and 151X for writes and reads respectively on the Perlmutter supercomputer.
The Message Passing Interface (MPI) has been widely used in distributed and parallel applications. Collective operations significantly impact the performance of applications. Broadcast is one of the most commonly used MPI collective operations for broadcasting data to all processes within a communicator. Modern interconnections have provided advanced capacity, such as offloading communication to the network to accelerate inter-node communication. However, the traditional host-based broadcast approach fails to leverage this feature. To fully offload the broadcast operation to the network, the semantic gap between MPI-level broadcast and hardware multicast of the underlying interconnects presents significant challenges. Additionally, in non-blocking communication, host-based collective operations often suffer from inefficient overlap between computation and communication. In this paper, we propose a hardware-software co-design to optimize MPI_Bcast and MPI_Ibcast. Our approach completely precludes the involvement of the CPU to accelerate inter-node communication by efficiently leveraging the NIC-based collective offload mechanism provided by Tianhe-Express interconnect. Meanwhile, it frees up a substantial amount of CPU resources from handling communication, allowing the CPU to execute useful computation. Therefore, our approach effectively increases the overlap between computation and communication in non-blocking scenarios. In addition, our approach can be adaptively tuned to achieve optimal performance across various message and system sizes. We further propose a topology-aware optimization to reduce inter-node overhead by constructing an optimal global communication tree, thereby enhancing the inter-node communication of our approach. Extensive experiments are conducted to evaluate the performance of the proposed algorithm at both the microbenchmark and application levels. Compared to state-of-the-art MPI libraries, at the microbenchmark level, our approach achieves a maximum speedup of 4.22 & times; and increases the overlap between communication and computation up to 79%. Meanwhile, our approach also achieves a 36% improvement for the application throughput.
With the proliferation of advanced vector instruction sets in modern CPUs, achieving performance portability for large Fortran-based scientific codes has become increasingly challenging. This paper focuses on CLOUDSC, a computationally intensive and data-access-complex cloud microphysics parameterization scheme in the Integrated Forecasting System (IFS) of ECMWF. We propose Auto-CLOUDSC, an auto-generation framework that optimizes CLOUDSC through the following approaches: (1) an auto-generator consisting of three modules-a function interface generator, a code structure analyzer, and an expression parser-to convert Fortran source code into vectorized instruction sets; (2) a physics-combine algorithm that applies loop fusion to reduce redundant memory accesses; and (3) a cache-aware algorithm that leverages cache tiling and data layout optimizations to enhance data reuse. Experiments demonstrate that the auto-generated code achieves a speedup of 1.3 to 2.1 times over the original Fortran baseline on the Phytium FT2000+ ARMv8 processor, and 1.9 to 3.4 times on the Intel Xeon Platinum 8358 processor.
Molecular Dynamics (MD) simulation is a computational technique that models system evolution at the atomic and molecular scale, bridging microscopic mechanisms with macroscopic phenomena. As research demands larger simulations, MD system sizes and computational requirements continue to grow. In large-scale MD, interatomic force calculations consume the majority of the computational time, making it highly compute-intensive and well-suited for supercomputers. LAMMPS is one of the most widely used MD software packages. In this paper, we present an optimization of the TIP4P (Transferable Intermolecular Potential 4 Points) water model implementation in LAMMPS on the new-generation Sunway supercomputer, which is the successor to the Sunway TaihuLight supercomputer. To fully exploit the architectural features and parallel computing capabilities of the Sunway processor, we design and implement efficient parallel algorithms for TIP4P force computation and neighbor list construction. Furthermore, we propose a series of synergistic optimization strategies: an AoS-based data layout strategy, a thread-private software cache method to write back discrete data, a shared Local Data Memory (LDM) scheme to enhance data reuse and reduce memory latency, and a fine-grained parallel force algorithm. Experiments show more than 10 & times; speedup on a single node, with 83.6%-88.2% parallel efficiency in weak scaling tests, demonstrating excellent scalability. Our approach significantly boosts performance on Sunway and provides a practical, generalizable optimization framework for large-scale MD simulations.
Several efforts have been made to study the nature of performance interference in co-allocated applications running in different environments. Such performance interference degrades the performance of co-allocated applications. Several researchers propose different methods and techniques to predict/analyze the performance of applications under different levels of interference. Hardware counters, virtual machine monitor metrics and third-party tools are commonly used to provide the input data for prediction techniques. The study of performance interference is useful for understanding, preventing, and minimizing application throughput degradation. This paper presents a systematic review of the literature on methods for predicting/analyzing performance interference that degrades application performance, which were published in the open literature during the period 2000-2025. We define two complementary classification frameworks. The first framework categorizes the analyzed articles according to the methods employed, while the second classifies them based on the platforms and tools used, along with other relevant characteristics. In addition, we identify some directions and trends in performance interference, as well as some issues that require further research. Finally, we propose a practical guide to help researchers and practitioners select methods and tools according to their needs.
