Recent advances in Language Models (LMs) enable conversational systems that interpret natural-language requests, select application actions, and generate user-facing responses. However, existing studies typically either examine complete assistants with limited deployment evidence or benchmark individual components in isolation. This work advances the state of the art through a unified cross-platform characterization of a local speech-to-text-LM-text-to-speech pipeline combining Moonshine, Piper, and four quantized LMs ranging from 1.2B to 8B parameters. The pipeline is deployed on an Nvidia Jetson AGX Orin, a Raspberry Pi 5, and an STM32MP257F-EV1, and evaluated in thermostat and washing-machine use cases. Action-selection capability is assessed on 200 labelled explicit and implicit requests per use case, while deployment is characterized through metrics such as memory footprint, speech Real-Time Factor, decoding throughput, power consumption, etc. Granite 3.3 (8B) achieves the highest Macro F1-scores, whereas Qwen3.5 (4B) provides the best capability–resource trade-off. Speech processing is faster than real time on the Jetson and Raspberry Pi, while the STM32MP2 supports smaller LMs in memory but is unsuitable for responsive CPU-only conversation. LM decoding accounts for over 90% of turn duration, and memory-Roofline analysis identifies model footprint, runtime support, response length, and streaming execution as the main optimization levers.
Memory bandwidth and intermediate buffering are major bottlenecks in high-throughput FPGA-based vision systems deployed on resource-constrained edge platforms. Stereo vision reconstructs 3D information by analyzing disparities between two-dimensional images. It is a representative workload that requires evaluating many disparity hypotheses while maintaining real-time performance and low power consumption. This paper presents a memory-efficient FPGA architecture for block-based stereo matching, demonstrated using a PatchMatch formulation. The proposed design employs a compact graph-based unary cost model that enables low-bit (2-bit) cost representation, together with a single-buffer cumulative cost architecture that eliminates multi-row buffering during block aggregation. These architectural choices result in a fully streaming dataflow with significantly reduced BRAM and LUT requirements. The system is implemented on a Xilinx Zynq UltraScale+ (xczu15eg) FPGA and achieves real-time processing at 192 FPS for Full HD (1920×1080) resolution with 128 disparity levels, operating at 400 MHz. The design delivers a throughput of 51,199 MDE/s while utilizing 43.7k LUTs, 50.1k FFs, and 169.5 BRAMs, corresponding to approximately 35% reduction in LUTs and 50% reduction in BRAMs compared with the baseline Block PatchMatch architecture. These results demonstrate that the proposed architecture effectively balances accuracy and hardware efficiency, providing a scalable and resource-efficient solution for high-throughput stereo matching on FPGA-based edge systems.
Recent advances in large language models (LLMs) have demonstrated strong capabilities in program processing tasks, motivating their application to visual programming languages (VPLs). However, VPLs are inherently graph-structured and rely on syntactic, structural, and semantic constraints, whereas LLM inputs may encode these interdependent properties only partially or implicitly, creating a representation mismatch. This paper systematically reviews a corpus of 41 studies published between 2022 and 2025, focusing on LLMs for executable VPLs. We introduce a graph-and-constraint framework that captures graph structure and constraints and use it to analyze target languages, representations, methods, and evaluation practices. Our analysis shows that linearized representations remain dominant. Only four studies use Multimodal Large Language Models (MLLMs) to process images or videos, and none conducts a controlled comparison with structured representations. Evaluation remains fragmented and lacks standardization. We identify key challenges in preserving explicit relations in serialized inputs, recovering implicit relations from visual cues, integrating constraints, addressing limited data. Together, these findings clarify the limitations of current approaches and inform the development and evaluation of more reliable LLM-based methods across heterogeneous VPLs.
Trusted Execution Environments (TEEs) leveraging ARM TrustZone are widely deployed in mobile, IoT, and industrial devices. Nonetheless, vulnerabilities are still being discovered/reported on these systems, highlighting ongoing risks. In this paper, we extend prior research on TrustZone vulnerabilities for Application processors (TZ-A) by presenting a comprehensive reassessment of TrustZone-assisted TEEs, analyzing 520 bug reports between 2019 and mid-2026. We systematically examine vulnerabilities affecting major TrustZone TEE implementations, including those from major commercial providers, e.g., Qualcomm, Huawei, and Samsung. We concluded that despite years of research and mitigations, existing TEE implementations continue to be victims of the same architectural, implementation, and hardware issues reported in previous work. Furthermore, we provide clear evidence that these vulnerabilities have also been propagating into TrustZone-M (TZ-M) TEEs, exposing similar security issues in modern microcontroller (MCU) environments. Our findings, based on publicly disclosed CVEs, security bulletins, and academic studies, reiterate the urgent need for the industry to adopt stronger security techniques and mechanisms proposed by academic research as a fundamental step toward trustworthy commercial TEE implementations.
With the rise of artificial intelligence, the autonomous navigation of robots has received widespread attention. The goal is to find the optimal or suboptimal path from the starting point to the destination while avoiding obstacles. In the Soft Actor-Critic (SAC) framework, maximum entropy regularization encourages the agent to explore more diverse actions. However, in complex navigation tasks with various obstacles, the increased dimensionality of the environment leads to increasingly complex state and action spaces. Common dimensionality reduction techniques reduce the dimensionality but inevitably lead to data loss. The local observability of the environment makes it impossible for the agent to obtain complete environmental information during the decision-making process, exacerbating the plasticity loss problem. To solve this problem, this paper proposes an intrinsic and diffusion contrast architecture (IDCAC), which is based on the introduction of intrinsic reward elements through external rewards. Additionally, it simulates various data by generating virtual data and using the deep diffusion contrast model for reward prediction. Finally, it assists in training by embedding the contrast learning features into the learning strategy. Since this problem is more likely to occur in high-dimensional environments, multiple experiments were conducted in static, dynamic, and mixed environments. The simulation results show that the higher the complexity of the environment, the higher the learning efficiency of IDCAC is, and compared with TD3, DDPG, SAC, PPO, and REDQ, it has fewer collision times.
The continuous emergence of speculative execution vulnerabilities has posed a significant threat to processor security in recent years. It is imperative for hardware architects to conduct a comprehensive analysis of pre-silicon CPU designs for these vulnerabilities. However, formally verifying a complete speculative attack is challenging, because an end-to-end attack chain involves trigger generation, transient execution, covert-channel encoding, and secret reconstruction, which can lead to severe state-space explosion. This paper proposes SpecVerif, a formal verification framework for detecting misprediction-driven speculative execution trigger mechanisms. The key insight of SpecVerif is to decouple the trigger phase of speculative execution from covert-channel construction and secret leakage during formal analysis, thereby reducing the length of the checked attack chain. This allows the framework to focus on identifying instructions or RTL mechanisms that can open a transient execution window, rather than proving end-to-end exploitability. To realize this insight, we introduce an instruction-oriented differential verification scheme and a PC-based operand injection mechanism that injects controlled differences into the instruction under verification. We evaluated SpecVerif on two open-source RISC-V CPUs, BOOM and CVA6. Experimental results demonstrate that SpecVerif can effectively identify instructions capable of triggering speculative execution and provide bounded non-reachability evidence for instructions that do not violate the security property. Moreover, the framework requires only minimal manual annotations from the user. Our analysis also reveals a new potential speculative execution trigger mechanism in CVA6, which we term Spectre-JT.
