In this paper we present an FPGA implementation of the ASCON-128 lightweight cipher employing a pipelined finite-state-machine design alongside a highly optimized sequential design. Experimental results demonstrate substantial improvements in throughput, silicon area utilization, and power consumption. Our novel pipelined FSM design on the Kintex-7 FPGA operates at an impressive frequency of 449.83 MHz while utilizing only 1067 slices and consuming 82 mW of power. In comparison, our sequential design achieves 289.85 MHz with 685 slices and 80 mW of power consumption on the same platform. In addition, we propose a cost-effective, high-performance hardware architecture designed to mitigate power analysis attacks. At its heart is a dynamic two-share masking scheme driven by a non-linear Fibonacci and Galois ring oscillator PUF-based true-random number generator. Compared with published FPGA implementations of ASCON-128, it outperforms state-of-the-art designs in both resource efficiency and power consumption. Our protected Kintex‑7 implementation achieves 399.98 MHz using 3155 LUTs (250 Mbps), utilizing 2.8 × fewer LUTs and delivering a 2.52 × higher operating frequency compared with the Kintex‑7 implementation reported in [16].
Provenance detectors commonly preserve anomaly evidence at event or graph level, whereas analysts investigate persistent entities and their causal relationships. This mismatch creates a representation gap between self-supervised prediction and investigation output. We introduce persistent node evidence as an investigation-oriented representation boundary for provenance streams. Each process, file, and network-flow identity maintains a fixed-width state updated from a bounded relational neighborhood, cumulative statistics, and elapsed time. Three self-supervised views test current-edge compatibility, recent target history, and within-window relation combinations, organizing decomposable event errors around long-lived entities. The representation is implemented with a compact 3.98 M-parameter neural core and bounded two-layer relational propagation without repeatedly encoding the accumulated provenance graph. Full-process memory additionally includes feature metadata and persistent runtime state. An optional normality-aware calibration learns recurring benign high-loss patterns from allowed normal roles and preserves raw and calibrated node rankings as separate views. Given a supplied investigation interval, a fixed provenance-constrained constructor expands ranked nodes into compact candidate chains. Across five Defense Advanced Research Projects Agency (DARPA) Transparent Computing collections, at least one candidate chain contains an exact annotated core or support identity in 12 of 13 successful attack chapters; the primary chain does so in eight. Complete scoring-process memory remains data dependent, calibration gains vary across collections, and the chain result measures conditional attribution rather than end-to-end attack discovery. The results support persistent node evidence as a bounded bridge from event prediction to precision-oriented offline investigation.
Current wireless environments are characterized by severe spectrum congestion and deliberate interference, exposing the limitations of traditional radio systems. This article presents an AI-enhanced software-defined radio (SDR) architecture implemented entirely on a field-programmable gate array and deployed on the PYNQ-Z2 platform, designed to perform real-time spectrum sensing and adaptive jamming mitigation. The proposed architecture implements an end-to-end processing chain comprising a 2048-point fast Fourier transform (FFT), log-power feature extraction, and a low-precision quantized neural network executed on the programmable logic with minimal processor involvement. Experimental results show an end-to-end latency of 2.1 ms, a classification accuracy of 94.5
Modern network environments involve evolving data streams with shifting feature distributions and emerging attack patterns, challenging conventional IDS that assume stationary data. This paper presents DR-IID, a drift-resilient incremental intrusion detection framework that adapts to non-stationary conditions while preserving prior knowledge and maintaining low false positives. DR-IID integrates cross-temporal feature alignment with severity-aware learning via a Mixture-of-Experts architecture to compute a Drift Severity Score (DSS) that quantifies distributional divergence. Based on this score, the system applies incremental updates for low-severity drift or targeted retraining for high-severity changes, while a Cross-Temporal Feature Alignment (CTFA) mechanism ensures representational continuity without full retraining. A unified objective balances plasticity and stability according to drift severity. Experiments on progressive intrusion benchmarks demonstrate improved adaptability, detection accuracy, and robustness over baseline models, offering a scalable solution for resilient IDS in evolving environments.
Deep Neural Networks (DNNs) have become central to modern signal and image processing systems. However, their high computational complexity imposes significant challenges for hardware implementation, particularly in terms of resource utilization, latency, and energy efficiency. Field-Programmable Gate Arrays (FPGAs) provide a promising platform for accelerating DNN workloads, offering parallelism and reconfigurability. Nevertheless, conventional HDL-based designs lack portability, while existing OpenCL flows often rely on heuristic exploration, leading to unpredictable performance and inefficient hardware utilization. To address these challenges, this paper proposes a metrics-driven predictive methodology for FPGA-based DNN acceleration using an OpenCL-based high-level synthesis framework. The proposed framework integrates profiling-driven kernel selection, computational intensity analysis, predictive performance modelling, and HLS optimizations into a closed-loop design flow. Quantitative models for speedup, throughput, loop latency, overlap efficiency, and BRAM feasibility are introduced to systematically guide architectural and optimization decisions prior to hardware deployment. The framework was validated on a Xilinx Zynq-7000 FPGA using MNIST and CIFAR-10 image classification benchmarks, two common image classification benchmarks. Experimental results achieved 97.81
