This paper introduces a novel design automation approach for securing Systems-on-Chip (SoCs) by natively integrating security as a primary optimization objective. Unlike existing design automation solutions that typically explore implementations for specific vulnerabilities, our method utilizes a purpose-built security metric specifically tailored for SoCs. Our optimization algorithm accepts a system specification (either as an application or an abstract SoC description) and generates a secured SoC architecture. This architecture enhances the regular SoC with an optimized security component. Optimization goals include critical metrics such as security, area, power, and latency, which are quantified as system risk. As a proof of concept, the proposed DSE of security tested three distinct security optimization strategies on a single system architecture: unrestricted resource and power utilization, restricted resource utilization, and restricted power utilization. The optimizer effectively returns all valid solutions that adhere to the user’s defined risk constraints, clearly showcasing the inherent trade-offs between optimized system risk, Look-Up Table (LUT) utilization, and power consumption. The results demonstrate how designers can leverage this tool to identify optimal security and anomaly detection solutions tailored to their specific system architectures. For instance, while the most secure solution might demand thousands of LUTs, our tool facilitates balanced decision-making by considering security alongside resource, power, and latency constraints. This allows designers to incorporate security directly into the design process.
Matrix multiplication underpins a wide range of compute-intensive workloads, from image processing to deep learning inference. This work presents a novel hardware accelerator architecture that combines Strassen’s algorithm, systolic array optimizations, and approximate computing to enhance efficiency in area and power. At the leaf recursion level of Strassen’s algorithm, conventional exact multipliers (EMs) are selectively replaced with approximate multipliers (AMs). To preserve accuracy in critical paths, time-shared EMs are retained, balancing efficiency with correctness. The accelerator is built around multiple $64 \times 64$ systolic arrays comprising 4096 processing elements (PEs). Each PE dynamically selects from ten available AMs, producing a vast discrete design space. To navigate this combinatorial complexity, we propose a Variational Autoencoder (VAE) that compresses PE-level approximation configurations into a compact latent space. A multi-objective evolutionary algorithm (MOEA) then searches this space to optimize hardware-level metrics (area, power, delay) alongside application-level performance indicators such as SSIM, PSNR, and classification accuracy. Our design maintains numerical stability across recursive layers, ensuring the practical realization of Strassen’s asymptotic advantage over conventional multiplication. Through MOEA-driven exploration, we identified accelerator designs that reduce hardware footprint by up to 33% and improve power-delay product by 21%, with only a 0.9% drop in CNN classification accuracy. By decoding latent codes back to full PE configurations, the VAE enables fast and high-quality exploration, generating a composite Pareto frontier of optimized designs. Overall, this framework demonstrates effective co-optimization of hardware efficiency and application accuracy, providing low-cost, high-performance matrix multiplication tailored for approximate computing workloads.
The growing need for additional primary memory capacity in data centers and exascale computing is driving the integration of DRAM and NVMs, which utilizes the advantages of both memory types and lessens the drawbacks of these memory types. To maximize main memory capacity and ensure efficient use of PCM, migrating write-intensive pages to DRAM enables better overall performance. Accurately identifying migration candidates is non-trivial: static threshold-based schemes either move pages at fixed intervals or, whenever write counts cross a preset cutoff, often misplace hot data. More sophisticated machine-intelligent methods (e.g., LSTM- or Attention-based predictors, Deep RL) can adapt to complex access patterns but incur prohibitive training and inference overheads for on-chip deployment. In this paper, we present a lightweight, online RL-based migration scheme: PEARL. PEARL is a tabular Q-learning/banditstyle algorithm that maintains per-page “confidence” (Q-value), updates based on the access patterns, and drives promotion to DRAM or eviction to NVM. The proposed method is validated against state-of-the-art threshold-based migration techniques using SPEC 2017 benchmark suite applications. The method improves performance by $6 \%$ and reduces total energy consumption by $16 \%$, demonstrating a practical path to higher performance and greater write endurance.
In this work, we first implement a computational statistics framework for the design optimization of common-drain complementary field-effect transistor (CFET). By using numerical device simulations in combination with statistical design of experiments (DOE) methodology-specifically the central composite design (CCD)-we construct second-order response surface model (RSM) for all targeted electrical characteristics of CFET. Both the adequacy and accuracy of each RSM are verified through normal residual probability plots and residual-sum-of-squares analysis. These validated models are further employed to optimize CFET performance for its circuit applications. By jointly considering threshold voltage, off-state current, on-state current, subthreshold swing, and drain-induced barrier lowering, the structural parameters of the CFET are tuned such that the predicted electrical characteristics approach the desired targets more effectively than that of the nominal design. Moreover, Device simulations of the optimized structures of CFET show strong agreement with the RSM-predicted values, confirming the robustness and accuracy of the developed models. This study represents the DOE-based RSM optimization framework for CFETs, and the formulated equations show highly predictive fidelity, providing a compelling and practical guideline for CFET design prior to high-volume manufacturing.
An industry-strength hybrid optimization approach, involving derivative-free global search followed by derivative-free local refinement, is proposed to solve the multi-dimensional problem of compact model parameter extraction and reduce its multi-objective nature while retaining the original device physical formulations. An intelligent transition method is employed to combine Differential Evolution and Nelder-Mead algorithms from a curated selection of machine learning-driven optimizer candidates, achieving better-fitting performance in various operating regions for the first time. Extraction results for compact models such as ASM-HEMT with 35 parameters and BSIM4 with 29 parameters in 3 steps show that a best-fit error of less than $0.2 \%$ is achieved with much less automatic extraction time of 1800 seconds compared to hours of global search alone and weeks of traditional manual parameter tuning. A new cost function is introduced to reduce sensitivity to outliers and introduce region-appropriate automatic weights while preserving device physical formulations. This approach helps reduce total optimization time by a factor of at least 2 X compared to global optimization alone and reduces dependency on modeling know-how.
