A 3.2 GOPS Multiprocessor DSP for Communication Applications

Williams, J.,Singh, K.J.,Nicol, C.,Sackinger, E.

San Francisco, CA, USA（2000）

Lucent Technol.

被引用17|浏览13

摘要

This programmable DSP is the first implementation of the scaleable-bus-based platform, Daytona for communication infrastructure equipment and broadband access terminals. An aggressive memory hierarchy minimizes bus traffic and meets the performance requirements for large multi-channel signal processing applications with the smallest possible memory footprint. The chip was implemented with full custom memories with 0.35 /spl mu/m features and the remaining logic is implemented with standard cells. The 207 mm/sup 2/ 0.25 /spl mu/m CMOS chip achieves 100 MHz and dissipates 4 W at 3.3 V.

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关键词

CMOS digital integrated circuits,digital signal processing chips,pipeline processing,programmable circuits,reduced instruction set computing,0.25 mum,3.2 GOPS multiprocessor DSP,3.3 V,32 bit,4 W,CMOS chip,Daytona for communication infrastructure equipment,RISC processor,aggressive memory hierarchy,broadband access terminals,communication applications,full custom memories,large multi-channel signal processing applications,memory footprint,power dissipation,programmable DSP,scaleable-bus-based platform,standard cells