A Low-Power Decoder for 1000BASE-T Transceiver Using T-Algorithm

Conventional Parallel Decision Feedback Decoder (PDFD) for $\mathbf{1 0 0 0}$ BASE-T transceivers, using Register Exchange Architecture (REA) in the Survivor Memory Unit (SMU), inherently suffers from high dynamic power consumption since the requirement to store and shift symbols for all possible paths at every decoding step, leading to massive register bit-flipping activity. To address this critical inefficiency, this paper leverages path pruning with the $\mathbf{T}$-algorithm to reduce the power consumption in SMU. The core innovation lies in integrating the T-algorithm to discard paths dynamically and deliver the enable signal to the ACSU (Add Compare Select Unit) and SMU. In SMU, these enable signals are used to gate the clock of SMU registers, effectively preventing the storage and unnecessary switching activity associated with pruned paths. These signals are also used in ACSU to eliminate redundant addition operations for discarded paths. Crucially, this power reduction is achieved without effecting BER performance. Synthesized with a 28 nm CMOS standard cell library, the results demonstrate that the proposed decoder achieves a significant 21% reduction in power consumption compared to a conventional PDFD.