A Programmable Power-Efficient Decimation Filter for Software Radios

EN Farag,RH Yan,MI Elmasry

International Symposium on Low Power Electronics and Design (ISLPED)（1997）CCF C

UNIV WATERLOO

被引用11|浏览0

摘要

Several high-level low-power design techniques have been incorporated in the design of a decimation filter for software radio. These include; operation minimization, multiplier elimination and block deactivation. Analysis and simulation results indicate that these techniques can achieve a 4 times reduction in power dissipation. An interleaved multiplier-accumulator array is used in the lowpass filter. The decimation filter designed has a programmable resolution, that varies from 12 to 20 bits. The entire decimation filter has been designed in a 3.3 Volt 0.5 /spl mu/m CMOS technology.

更多

查看译文

关键词

CMOS digital integrated circuits,VLSI,digital filters,digital radio,low-pass filters,programmable filters,radio receivers,0.5 micron,12 to 20 bit,3.3 V,CMOS technology,block deactivation,high-level low-power design techniques,interleaved multiplier-accumulator array,lowpass filter,multiplier elimination,operation minimization,power dissipation reduction,power-efficient decimation filter,programmable power-efficient decimation filter