A Resource-Adaptive, Highly Parallel Hardware Accelerator for CNNs on ZYNQ-7000 SoC

With the advancement of artificial intelligence and the Internet of Things, the demand for deploying neural networks on embedded devices is steadily increasing. Field Programmable Gate Arrays (FPGAs) are an optimal solution for this challenge due to their low power consumption, low latency, and programmability, which has garnered significant attention in the industry. This paper proposes a hardware accelerator architecture that leverages both the Processing System (PS) and Programmable Logic (PL) sides in parallel, based on the ZYNQ-7000 series System on Chip (SoC), and demonstrates its superior performance through the deployment of multiple convolutional models.