A Second Level Data Buffer with LHC Performance

For the ATLAS experiment at the Large Hadron Collider (LHC) buffers are required which will accept data at rates in excess of 100 Mbytes/s and distribute selected data to the second and third level trigger systems. A design for a buffer using a digital signal processor as the memory manager is described and the performance of a prototype module is given. Tests of the system in a beam line will be used to develop and check discrete event simulation models of the buffers and a second level trigger system.