A Secure Scan Technique to Withstand Side Scan Channel Vulnerabilities

ABSTRACT Design for Test (DFT) enhances the reliability of integrated circuits (ICs). However, the use of scan‐based methodologies exposes internal nodes within ICs to possible side‐channel attack vectors. This paper proposes a novel secure architectural framework around the DFT logic to protect against SCA and other forms of confidential data leakage from the chip. This novel architecture implemented is a Low‐Power Q‐gate Secured Scan Register (LP‐Q‐SSR), that bridges the gap of traditional scan‐based designs that reduces the toggling activity, power usage and secures the chip. The proposed design incorporates improved low‐power design with Linear Feedback Shift Register (LFSR) driven mux flop which is a counterpart of conventional scan methodology incorporating the Q‐gating and X‐filling techniques to maintain the design test, power and security conscious. It uses Multi‐Polynomial Asymmetric Dual (MP‐Asym Dual) LFSR and its tapping mechanism to control the scan data flow and uses test strategies like Q‐gating technique and X‐filling algorithm for optimizing the power. This makes the hackers difficult to encrypt the test‐mode and to fetch the confidential data of an IP or IC or SoC. The proposed secured scan architecture demonstrates significant improvements over the conventional scan‐based architecture, achieving ∼1.81× reduction in test pattern count, ∼5.45× faster runtime, ∼27.13% lower switching activity, and ∼50.9% power savings while supporting a 128‐bit design. Additionally, the architecture enhances testability (∼1.5%) and memory efficiency (∼1.25×) with minimal area overhead of only ∼2.17%, highlighting its effectiveness for low‐power and secure VLSI testing.