A Single-Cycle, Area-Efficient Calibration Method for TDC-based Timing Monitors

Modern System-on-Chips (SoCs) increasingly integrate time-to-digital converter (TDC) based on-chip timing monitors to enable self-awareness for dependability-related applications. These monitors offer sub-clock cycle resolution but are highly sensitive to on-chip variations such as process, voltage, and temperature (PVT), transient voltage droop, and long-term selfaging effects. As a result, in-field calibration of these monitors becomes inevitable for achieving reliable measurements. This paper proposes a fast, single clock cycle calibration methodology that enables simultaneous calibration of multiple TDC-based timing monitors operating in the same voltage domain in an SoC. The novelty of this approach lies in the use of a shared, per-voltage-domain calibration IP instead of per-monitor selfcalibrating logic, which significantly reduces the area overhead associated with a monitoring infrastructure. Furthermore, the proposed IP is suitable for calibration against fast-changing phenomena like voltage droop as well as slower variations like PVT and aging. In addition to the conventional TDC-based positive slack monitor, design for a negative slack monitor is also discussed, which estimates negative slack during late signal transitions by sampling the transitioning signal immediately after the capturing clock edge. This enables in-field estimation of both positive and negative slack, supporting adaptive mechanisms for resilient system operation. Post layout evaluation of the proposed IP and the timing monitor is presented using the TSMC 65 nm standard cell library. Results demonstrate that the proposed calibration method reduces the average magnitude of error (RMSE) in slack measurement by 46%.