Even with simulation and formal verification techniques, some bugs reach the silicon, thus, nowadays post-silicon debug techniques are vital for the fabrication of reliable integrated circuits. One approach used is the assertionbased design, in which an assertion processor (AP) can be employed to monitor synthesized property checkers. To reduce area overhead and provide more flexibility through the project stages, in this paper an external AP is implemented using a softcore processor and embedded software. A case study of the architecture using a MIPS32 based processor is also discussed. The area of the synthesized processor with the structure needed to connect itself to the external AP presented an increased of only 0.5%. Furthermore, the implementation costs of the proposed architecture are analysed.
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