A Switch Cache Design for MIN-Based Shared-Memory Multiprocessors

In this work, we investigate the idea of incorporating caches into selected switching elements of a multistage interconnection network (MIN)-based multiprocessor. Along with the processor private caches, these switch caches form a two-level cache hierarchy. Selected switch caches within a particular stage of the MIN are connected by a coherence control bus, through which a write-invalidate cache coherence protocol maintains coherence of private and switch caches. The impact of the protocol on system performance is evaluated through a simulation-based performance study, which shows that it is feasible to build large shared-memory cache-coherent multiprocessor systems.