A Testability-Driven Technology Mapping Method for Optimized Test Point Insertion

Test point insertion (TPI) is an effective design-for-test (DFT) technique for improving circuit testability. However, conventional TPI is typically applied after logic synthesis and often incurs area and timing overhead. Technology mapping, a critical phase in logic synthesis that converts technology-independent logic networks into standard-cell implementations, provides an opportunity to address this limitation earlier in the design flow. Nevertheless, existing technology mapping methods do not consider testability and are thus not well-suited for TPI. This paper proposes a novel testability-driven technology mapping method to improve the efficiency of TPI. Test point analysis is performed on the And-Inverter Graph (AIG), and the resulting information is used to guide the subsequent TPI-oriented matching stage. Delay-oriented and area-oriented matching are then applied to further optimize timing and area in the final netlist. Experimental results demonstrate that the proposed approach achieves testability comparable to that of the conventional method while requiring fewer test points and a smaller area. For automatic test pattern generation (ATPG) pattern count reduction, it reduces the test point count by an average of 23.65% and the area by an average of 2.80%. For logic built-in self-test (LBIST) test coverage improvement, it achieves average reductions of 20.02% in test point count and 3.47% in area.