An Adaptive Write Back Method for on Chip Cache

In this paper, we introduce a novel write back method named as the adaptive write back method to solve a memory bottleneck problem and to reduce power consumption. The key of this architecture is adaptively changing the timing of write back operation to an external memory. As a result, the proposed architecture can alleviate the memory bottleneck problem by preventing intensive memory accesses. Also we can reduce the peak power which is a critical problem for embedded systems. We have evaluated the new proposed method on 3D graphics pixel cache on a SoC environment in where various IPs are embedded. The simulation results show the effectiveness of the proposed method.