Interference within a multi-core architecture may have several origins. Understanding where interference comes from is mandatory for verification and certification purposes. Unfortunately, the complexity of current architectures makes it difficult to quantify such interference. In this article, a new approach is introduced that enables benchmark configurations to isolate and quantify interference. An experiment with DMA interference is presented and shows a WCET overhead of up to 0.26% at 25 Mbit/s. This experiment was also able to discover and identify interference related to DMA, such as interruptive flow overhead, around 3% for 25 Mbit/s, or packet transmission memory access overhead, around 9% for 25 Mbit/s.
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adaptation,cyber-physical systems,design space exploration,resilient control