Automatic Cell-Aware Software-Based Self-Test Generation for a RISC-V Core Local Interrupt Controller

Software-Based Self-Tests (SBST) allow for at-speed testing of on-chip devices via a processor core. However, creating SBSTs requires time-consuming manual labour that is expensive and requires in-depth knowledge of the device’s architecture for targeting hard-to-test faults. Introducing cell-aware testing to this task further exacerbates the necessary effort. In contrast, automating the complex parts of SBST generation using Bounded Model Checking (BMC) allows using sophisticated, state-of-theart BMC solvers to automatically generate vast parts of the SBST. Thereby, a virtual circuit called Validity Checker Module (VCM) is used to encode constraints for the SBST. In this paper, we focus on generating a cell-aware SBST for a Core Local Interrupt Controller (CLIC) that is executed via a RISC-V processor core. We first d erive a constraint s et that creates SBST-like conditions during ATPG, which allows for transformation into instructions later on. We implement a cellaware test model via a re-entrant Mealy state machine that allows complex behaviors of the faulty cell. Experimentally, we extend the CLIC with a test interface that is controlled via a custom CSR of the processor core to reduce SBST generation time and enhance fault coverage. We conclude with the evaluation of our approach on the PULP CLIC implementation that shows cellaware SBST generation to be feasible while achieving acceptable fault coverages and practical generation runtimes.