Hardware verification of the register transfer level (RTL) designs is a critical step in the development of complex digital circuits, ensuring their functional correctness, performance, and reliability. Within this crucial process, bug localization is an essential component for precisely identifying the root causes of design errors. Dynamic bug localization (DBL) stands out as an efficient and automatic approach to locate bug source code by calculating statement suspiciousness based on execution traces. However, DBL methods rely solely on coverage information and simplistic statistical formulas to compute suspiciousness, which has been criticized for their limited precision and inadequate reduction of debugging effort. In this paper, we propose MulFetFL: a multi-features deep learning based bug localization for RTL designs. MulFetFL begins by extracting three multimodal features: abstract syntax tree (AST) features, signal features, and timing features from designs. It then employs Graph Attention Networks (GAT) to enhance node representations. A cross-modal attention mechanism is subsequently applied to fuse these complementary features from different modalities. Finally, the fused features are passed through a multi-layer perceptron (MLP) to compute the suspiciousness score for each statement. Experimental results show that MulFetFL effectively locates 293, 295 and 298 bugs within Top-1/Top-3/Top-5 ranks, significantly outperforming state-of-the-art bug localization methods across a range of benchmark designs.
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