Cache Side-Channel Attacks Detection for AES Encryption Based on Machine Learning

Contemporary research on cache side-channel attack detection frequently emphasizes accuracy while overlooking crucial factors such as overhead and detection speed. In response to these challenges, we analyze the combined effect of detection speed on system loss and detection accuracy. We find that increasing the hardware event sampling rate not only results in excessive system loss but also decreases the accuracy of constructed cache side-channel attack detection. In this paper, we verify on different hardware platforms that establishing a critical hardware event sampling interval is essential for constructing effective attack detection. This allows for the quick and accurate identification of three cache side-channel attacks while keeping system overhead low. Through experiments, we determined that the critical hardware event sampling interval for the two hardware platforms used in this paper is close to 500 us. The accuracy of the attack detection constructed on the I5-7200U platform finally reaches 97.39