Capacitorless Double-Gate Junctionless 1T DRAM Using Comb Structure

Abstract This work proposes a novel double-gate (DG) junctionless (JL) capacitorless dynamic random access memory (1T-DRAM) by combining a trench-isolated channel and a high-k gate dielectric (TiO2) to improve the performance metrics of the memory cell. The trench-isolated channel architecture design, formed by incorporating SiO2 filled comb structures within the silicon body, improves charge confinement and reduces recombination, thereby increasing retention time (Tret) and sense margin (SM). Comprehesive TCAD simulation results show that significant improvements in retention and sensing characteristics. The device achieves a Tret of ∼ 179 ms and a SM of ∼14.84 μA/μm at 27 ◦C. Also, with increase in temperature of 85 ◦C, it maintains a Tret of ∼10 ms and an SM of ∼10.27 μA/μm, indicating robust thermal stability. This enhanced electrostatic integrity of the DG JL structure further reduces short channel effects (SCEs) and improves data reliability.