Characterising Physical Memory Access Pattern Impact on RISC-V Softcore Performance: A Microbenchmark Study

Modern processor performance is strongly constrained by the memory hierarchy and memory access patterns, and this sensitivity is particularly pronounced for FPGA-based soft-core CPUs with configurable memory subsystems. This paper presents a systematic experimental study of how physical memory access patterns interact with DRAM controllers and cache hierarchies to shape the performance of RISC-V soft cores on FPGA platforms with DDR4 memory. We evaluate representative access patterns including row-major sequential, column-major, small and large strides, and blocked traversal across STREAM kernels, dense matrix multiplication and transpose, and vector reduction workloads. The analysis compares an in order Rocket core and an out-of-order BOOM core instantiated on a Xilinx VCU118 board, using only standard RISC-V hardware performance counters to ensure portability. Row-major scans attain up to 163.91 MB/s on BOOM, while column-major traversal and large strides can increase per-element execution cost by up to 68 × speedup for matrix multiplication by keeping working sets within the 32 KB L1 cache, largely independent of core microarchitecture. Contrary to the common assumption that out-of-order cores are always more sensitive to memory pressure, we find that BOOM’s overhead can be higher or lower than Rocket’s depending on the workload, despite identical L1 caches and DRAM interfaces. The proposed microbenchmark suite and methodology form a reproducible framework for characterising memory-subsystem behavior of FPGA-based RISC-V systems and provide practical guidelines for designing locality-aware kernels on reconfigurable platforms.