Compact Iterative FPGA Camellia Algorithm Implementations

D Denning,J Irvine,M Devlin

Proceedings 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat No04EX921)

Inst Syst Level Integrat

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摘要

We present various iterative Camellia encryption algorithm implementations. The algorithm uses a 128-bit key, which keeps the algorithm as small as possible. The purpose for this implementation is for low-cost or area-restricted implementations suitable for embedded or mobile applications. We discuss the design and implementation considerations for a feedback architecture and achieve a throughput of 426Mbits/sec without key scheduling and 388Mbit/sec with key scheduling.

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关键词

cryptography,embedded systems,field programmable gate arrays,mobile computing,128 bit,128-bit key,388 Mbit/s,426 Mbits/s,embedded applications,feedback architecture,iterative Camellia encryption algorithm,iterative FPGA Camellia algorithm implementation,key scheduling,mobile applications