Design and Performance Analysis of New Metal Strip Incorporated Dual Oxide Dual Tunnel FET Evaluating Trap Charges for Augmented Reliability

An abrupt tunnelling intersection needs to exist for a TFET (tunnel field effect transistor) to operate with outstanding electronic and switching capabilities. Additionally, reliability challenges resulting from trap charges created during TFET manufacturing need to be addressed for TFET design. This study examines the dependability of the suggested DGO (dual gate oxide) Tunnel FET centred around bilateral tunnelling (BT-TFET) incorporating low work-function metal strip (LWMS) for the first time. Sharp tunnelling interface at the channel and source conjunction is generated by administering LWMS in the dielectric with high-k region near the source, thereby benefitting threshold voltage (Vth) and subthreshold swing (SS). Furthermore, the gate dielectric's dual oxide promotes the capacitance interaction involving the gate and the dielectric, strengthening the device's quality and dependability features. The recommended LWMS-DGO-BT-TFET demonstrates a diminished Vth of 0.6 V, a superior ON to OFF state current proportion of 1013, and a dropped SS of 14.7 mV/decade. The dependability of the suggested device has been investigated by assessing the repercussions of positive as well as negative traps on various metrics such as static or DC, RF/analogue performance statistics, consisting of electric field, transfer metrics, transconductance (gm), and so forth, of the suggested LWMS-DGO-BT-TFET and the original single gate oxide bilateral tunnelling TFET incorporating LWMS (LWMS-SGO-BT-TFET). Beyond that, contrasting evaluation of both of these designs was additionally conducted with respect to distortion statistics comprising third-order voltage intercept point (VIP3), second-order and third-order transconductance coefficients. Research has shown that positive traps lift the ON-current of the suggested design by 7.38