Efficient Dynamic IC Design Analysis Using Graph-Based Semi-Supervised Learning

Graph analysis in large integrated circuit (IC) designs is an essential tool for verifying design logic and timing via dynamic analysis (DA). IC designs resemble graphs with each logic gate as a vertex and the conductive connections between gates as edges. Using DA digital statistical correlations, graph condensation, and graph partitioning, it is possible to identify anomalies in high-entropy component centers (HECCs) and paths within an IC design. Identification of HECC aids in DA signal integrity analysis when comparing design iterations which effectively lowers the computational complexity of DA within large IC graphs. In this paper, a devised methodology termed IC layout subgraph component center identification (CCI) is described. For design deviation analysis in DA, CCI lowers design computational complexity by identifying design deviations within an IC's subgraphs. The CCI logic function signal integrity is verified using semi-supervised learning consisting of an unsupervised autoencoder anomaly detector to first identify anomalous subgraphs followed by efficient subgraph iterative refinement to locate specific deviated logic signals within the subgraphs.