Evaluation Tool for Stencil Application Memory Usage.

Iterative stencil loops are a widely used class of matrix algorithms, with applications in the fields of image processing, neural networks, scientific computing, and mathematics. They are, however, very vulnerable to memory bottlenecks from reading large amounts of repeated data. This paper aims to study the cache usage of stencils, and proposes an implementation of the data-locality management unit (DMU) as a tool accelerate stencil execution. The DMU is a programmable memory controller for managing main memory reads and data reorganisation. Finally, this paper uses simulated behavioral models of the architecture to examine the effect of the DMU on both memory reads and CPU load. Initial tests showed a reduction of 50% in both CPU instructions and DRAM loads when using the DMU, when compared to unoptimised stencil code, and a similar reduction in memory reads even compared to highly optimised stencil code.