Extended Buffer-referred Prefetching to Leverage Prefetch Coverage

This paper is an extension of the work originally presented in the 26th International Conference on Automation and Computing.This study regarding hardware prefetching aims at concealing cache misses, leading to maximizing the performance of modern processors.This paper leverages prefetch coverage improvement as a way to achieve the goal.Original work proposes two different storage buffers to enhance prefetch coverage; block offset buffer and block address buffer.The block offset buffer updates its contents with the offsets of a cache block accessed, while the block address buffer contains the address of a cache block prefetchissued.The offset buffer is utilized to speculate a local optimum offset per page.The offset buffer is proposed to adopt multiple lengths of delta history in observing offset patterns from completely trained table.This paper advances to employ incompletely trained table as well, while in other prefetching methods including original work, only completely trained candidates are utilized.Furthermore, we construct the table on the fly.Rather than using only completely built tables, we offer utilizing and updating table concurrently.This paper also proposes a refined metric from existing prefetch accuracy metric, to measure net contribution of a prefetcher.Compared to the original work, we have 2.5% and 3.8% IPC speedup increment with singleand 4-core configuration, respectively, in SPEC CPU 2006.In SPEC CPU 2017, our work achieves 4.5% and 5.5% IPC speedup improvement with single-and 4-core configuration, respectively, over the original work.Our work outperforms the 2nd best prefetcher, PPF, by 2.9% and 2.7% IPC speedup with single-and 4-core configuration, respectively, in SPEC CPU 2006.In SPEC CPU 2017, our work surpasses both Berti by 1% and SPP by 2.1% IPC speedup with 4-core configuration in SPEC CPU 2017.