First Results with Prototype ISIS Devices for ILC Vertex Detector

The vertex detectors at the International Linear Collider (ILC) (there will be two of them, one for each of two general purpose detectors) will certainly be built with silicon pixel detectors, either monolithic or perhaps vertically integrated. However, beyond this general statement, there is a wide range of options supported by active R&D programmes all over the world. Pixel-based vertex detectors build on the experience at the SLAC large detector (SLD) operating at the SLAC linear collider (SLC), where a 307 Mpixel detector permitted the highest physics performance at LEP or SLC. For ILC, machine conditions demand much faster readout than at SLC, something like 20 time slices during the 1 ms bunch train. The approach of the image sensor with in-situ storage (ISIS) is unique in offering this capability while avoiding the undesirable requirement of ‘pulsed power’. First results from a prototype device that approaches the pixel size of 20 μm square, needed for physics, are reported. The dimensional challenge is met by using a 0.18 μm imaging CMOS process, instead of a conventional CCD process.