FPGA-Based 2-Phase Asynchronous Circuit Design for High Performance Computing

This work explores the design methodology and FPGA-based realization of asynchronous circuits composed of static data-flow handshake components governed by the two-phase bundled-data (BD) protocol. The methodology integrates tutorial-driven exposition with formal architectural analysis, emphasizing a rigorous approach to initialization strategies and the construction of coupled ring structures with arbitrary token distributions. Central to the design flow is the use of Mousetrap-style control templates, enabling localized, transition-driven handshake logic. The paper substantiates its methodology through a comprehensive power-performance-area evaluation, including gate-level synthesis of core handshaking primitives in a 32 nm CMOS technology node. Furthermore, it incorporates peephole-level optimizations, wherein composite components such as merged Join-register or MUX-register structures are synthesized for improved design efficiency. The practicality of the design flow is ultimately validated through the implementation of a Fibonacci sequence generator, showcasing correct functionality and handshake compliance across all components. All modules and the target circuits are verified through full-system deployment on Xilinx Basys 3 FPGA board, confirming robustness and functional correctness of the protocol under real hardware conditions. The average PPA metric of the Mousetrap controller has improved to 38%.