FPGA Implementation of Trigonometric Function Using Loop-Optimized Radix-4 CORDIC

Trigonometric operations have a wide range of use in communication, signal processing, and especially in computer science. Many methods exist to implement these functions on hardware, but complicated algorithms lead to high hardware consumption and latency. This paper presents a design to perform trigonometric calculations on FPGA that can be processed in parallel to reduce latency. We propose loop-optimized Radix-4 CORDIC algorithm for hardware implementation. This algorithm uses only three iterations to compute high accuracy trigonometric values. Besides, we apply multiply-less hardware architecture for the design, which consists of three basic operations: adders, subtractors, and bit shifters. The design is implemented on the Zynq™-7000 AP SoC kit XC7Z020-CLG484-100 device. The performance results show that the output returns values with absolute error lower than 0.005 after three clock cycles.