GPU Cache Flush Minimization in Render Graph Systems

Modern graphics APIs expose control over the infamously non-coherent GPU caches to application programmers through the mechanisms of pipeline barriers and render passes. A developer is then asked to group together their GPU computations based on memory access patterns such that cache flushes and invalidations are minimized, but render graph systems enable automation of this process. In this paper, we study the problem of finding an optimal execution order for a frame graph to minimize the amount of render pass breaks, which in turn minimizes cache control operations. We formulate and analyze a novel $NP$-complete problem $lang{MLGP}$ and use it to propose an approach to render pass merging that results in 30\% less render pass breaks when compared to previous works.