Hardware Implementation of OTFS Modulation Using CORDIC Algorithm

As per the existing literature, Orthogonal Time Frequency Space (OTFS) transceiver can be implemented using two different methods: i) the two step approach: includes inverse symplectic fast Fourier transform (ISFFT) and Heisenberg transform at the transmitter, along with SFFT and Wigner transform at the receiver, and ii) the direct approach: incorporates Inverse Zak (IZak) transformation at the transmitter and Zak transformation at the receiver. In this work, to expedite the implementation process of the OTFS transceiver in real-time wireless communication, we use field programmable gate array (FPGA) technology, leveraging the time acceleration benefits it provides. Additionally, while implementing the two aforementioned approaches, we employ the coordinate rotation digital computer (CORDIC) algorithm as it is flexible and requires minimum area. We compare the hardware performances among these two approaches in terms of resource utilization, timing, and power by implementing on the 7a200tiffg1156-1L FPGA board. We observe that, the direct approach exhibits significant improvements, with a 47.57% reduction in Look-Up Tables (LUTs) and a 17.63% reduction in Flip Flops (FF) compared to the two step approach in the OTFS transceiver design.